Commit Graph

66 Commits

Author SHA1 Message Date
4bae5c418b fix register use in putstring
was off by one, the syscall is write 
and the first arg is file_descriptor
ie 1 == stdout
2020-03-26 11:24:56 +02:00
bc558d1f0d do not copy name of method
so that the resolve can compare name identity
which is what is does, not equality
this (and some other bug) is crashing arm currently
2020-03-25 12:43:57 +02:00
90935bfbbc risc is GREEN
totally, man.
Small fix in method missing fixed last block tests
(why, i do not know)
2020-03-22 15:58:19 +02:00
ddd1f4e296 fix interpreter syscall and rename return reg
returned int for puts was same name as implicit return  int
2020-03-22 14:31:43 +02:00
fea98979e8 Fix comparison bug
Unchanged high level test, ohh how great is testing
2020-03-22 14:31:43 +02:00
0ed5e74748 Fixing ripples from previous 2020-03-22 14:31:43 +02:00
3ce6ed5263 fix putstring and puts
using syscall regs
2020-03-22 14:31:43 +02:00
3b50fee158 fix stray misc in slot 2020-03-22 14:31:43 +02:00
7232c28ecd operator also fell into ssa trap
relying on register identity
in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue
better now
2020-03-22 14:31:43 +02:00
3145547315 init fell into the ssa tap, fixed
reducing and assuming the same register, buuh
adds a transfer instruction that can hopefully be removed by analysis
2020-03-22 14:31:43 +02:00
5b0c1195e4 Fix interpreter and resolve method
Interpreter was not handling ssa correctly (ie overwriting)
Resolve was assuming wrong registers (also non ssa)
return value still broken
2020-03-22 14:31:43 +02:00
4db71c1c03 fix all uses of operators now they are ssa 2020-03-22 14:31:43 +02:00
f2250bc206 fix resolve and introduce method to chop strings to max
strings are 20 bytes. I want to implement the extension idea, just not now
2020-03-22 14:31:43 +02:00
126466e9a9 fixing tests 2020-03-22 14:31:43 +02:00
504fc3509e fix set_internal_word register 2020-03-22 14:31:43 +02:00
5c13ea1433 fix naming mistakes fo Word.get/set macros 2020-03-22 14:31:43 +02:00
d125a1528a Fix set_internal_byte registers 2020-03-22 14:31:43 +02:00
17a1121408 fix putstring registers 2020-03-22 14:31:43 +02:00
3a3a9277b3 fix operators registers 2020-03-22 14:31:43 +02:00
8867d60c13 fix method_missing register
logic is still wrong, even it is slightly less (at least loading the method name)
2020-03-22 14:31:43 +02:00
ede103e73d finally did assert_function_call
for cleaner reading, like all other instruction asserts
2020-03-22 14:31:43 +02:00
cf5a3c0102 fix inits registers
surprisingly easy. shorter code and more readable tests
2020-03-22 14:31:43 +02:00
7d8ef8ef64 fix allocate tests
as allocate got one smaller
2020-03-22 14:31:43 +02:00
8abcaa330b fix allocate in builder
which accessed unknown types.
also moved assert_allocate to support
2020-03-22 14:31:43 +02:00
8119030ed2 fix return sequence
broken due to logic error in register_slot << (which was reducing the wrong register, self, not the arg)

Still the sequence is in 2 places, one too many ?
2020-03-22 14:31:43 +02:00
05ddc70fd6 fix get_internal word register names
seems previous commits broke the return
2020-03-22 14:31:43 +02:00
a70e510548 fix test_exit registers 2020-03-22 14:31:43 +02:00
fb4fa598f2 fix get_internal_byte
improved operators and tests
some logic errors still
2020-03-22 14:31:43 +02:00
a70f63e7bb fix remaining slot instruction tests 2020-03-22 14:31:43 +02:00
07873ce068 fix not same logic
caused by assert logic error, also fixed
2020-03-22 14:31:43 +02:00
c1cfc12a1c converted resolve_method
Big, left till last, but surprisingly painless
2020-03-22 14:31:43 +02:00
28e9cd335a still fixing instruction tests 2020-03-22 14:31:43 +02:00
e6729b8b60 fixing instruction tests 2020-03-22 14:31:43 +02:00
22d513d895 fix div4 and tests
also bug in reduce_int, compiler not carried through
2020-03-22 14:31:43 +02:00
eed9ba082f Fix div10 and test
fix and use load_data (similar to load_constant)
and integrate into load_object when appropriate (ie for integers)
2020-03-22 14:31:43 +02:00
3ec5557ddb fix builder logic error
and tests
2020-03-22 14:31:43 +02:00
1760b5b203 fix comparison test and helpers
moving to passing the instruction number, not the instruction
so in the error message we can say where the error is
(otherwise minitest is good enough to supress the trace of asserts calling asserts)
2020-03-22 14:31:43 +02:00
3575aada17 tests for all macros
generated on master (know to work)
but with rXX registers, needs fixing
2020-03-22 14:31:43 +02:00
9c5d17a3bb Fix div10 without method_missing
but reanimate infer_type to auto create the needed regsiters
also some helpers
2020-03-22 14:31:43 +02:00
3688c967d3 Fix comparison macro
which leaves a definite need for instruction level testing
2020-03-22 14:31:43 +02:00
2af953e1d2 last instruciton, dynamic_call
next macros
2020-03-22 14:31:43 +02:00
7f5ebab800 did block yield 2020-03-22 14:31:43 +02:00
a4c0b8e5f9 did return sequence
surprisingly easy. also some check polish
2020-03-22 14:31:43 +02:00
db5a59f735 Unify instruction namings also dirs
Was getting confused myself, where it was instruction or instructions, when if the base class was inside or out of dir.
Now dirs are plural, and base class is inside.
2020-03-22 14:31:43 +02:00
f3d299208e fix message_setup with new builder 2020-03-22 14:31:43 +02:00
d0036ed95b better way to test object registers
also some cleaning, by using more helpers
2020-03-22 14:31:43 +02:00
ff49ff50c0 Convert SimpleCall to new regs
Also fix bug in RegsiterValue/Slot with chain, where logic was dodgy and compiler not set
2020-03-22 14:31:43 +02:00
4b303977a7 Fix first Slot instruction that uses builder
now without method_missing and names
but still with instance_eval, hmm. Tried without, makes code much less readable
2020-03-22 14:31:43 +02:00
4888b3b6db Starting to rework slot instructions that create risc
have to go through all and all macros and all thems tests. What did the wise man say: one step at a time
2020-03-22 14:31:43 +02:00
64d860b2bf create a load on the compiler
thus removing the need for << with objects on RegisterValue
2020-03-22 14:31:43 +02:00