fix stray misc in slot

This commit is contained in:
Torsten 2020-03-15 17:58:56 +02:00
parent 9f609bdb06
commit 3b50fee158
5 changed files with 18 additions and 16 deletions

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@ -4,10 +4,11 @@ module SlotMachine
builder = compiler.builder(compiler.source)
integer_tmp = builder.allocate_int
builder.build do
integer_1 = register(:integer_1)
object = message[:receiver].to_reg
integer = message[:arg1].reduce_int(false)
object <= object[integer]
integer_tmp[Parfait::Integer.integer_index] << object
integer_1 <= object[integer]
integer_tmp[Parfait::Integer.integer_index] << integer_1
message[:return_value] << integer_tmp
end
return compiler

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@ -5,7 +5,7 @@ module Risc
include Ticker
def setup
@preload = "Word.get"
@preload = "Word.get_byte"
@string_input = as_main("return 'Hello'.get_internal_byte(0)")
super
end
@ -14,13 +14,13 @@ module Risc
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5
RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10
SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15
SlotToReg, LoadConstant, OperatorInstruction, IsNotZero, SlotToReg, #20
LoadConstant, SlotToReg, OperatorInstruction, IsNotZero, SlotToReg, #20
RegToSlot, SlotToReg, SlotToReg, SlotToReg, ByteToReg, #25
RegToSlot, RegToSlot, SlotToReg, RegToSlot, Branch, #30
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #35
SlotToReg, Branch, SlotToReg, RegToSlot, SlotToReg, #35
SlotToReg, FunctionReturn, SlotToReg, RegToSlot, Branch, #40
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #45
SlotToReg, FunctionReturn, Transfer, SlotToReg, SlotToReg, #50
FunctionReturn, Transfer, SlotToReg, SlotToReg, Transfer, #50
Syscall, NilClass,] #55
assert_equal "H".ord , get_return
end

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@ -75,7 +75,7 @@ module Risc
end
def test_tick_26_exit
# 26.times { @interpreter.tick ;puts @interpreter.instruction.class}
ticks(26)
ticks(27)
assert_equal Syscall , @interpreter.instruction.class
assert_equal :exit , @interpreter.instruction.name
end

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@ -15,7 +15,7 @@ module SlotMachine
assert_equal Risc::MethodCompiler , @method.to_risc.class
end
def test_risc_length
assert_equal 38 , @method.to_risc.risc_instructions.length
assert_equal 39 , @method.to_risc.risc_instructions.length
end
def test_allocate
assert_allocate
@ -26,14 +26,15 @@ module SlotMachine
assert_transfer a + 2 , :message , :saved_message
assert_slot_to_reg a + 3 ,:message , 5 , :message
assert_slot_to_reg a + 4 ,:message , 2 , "message.data_1"
assert_syscall a + 5 , :exit
assert_slot_to_reg a + 6 ,:message , 5 , "message.return_value"
assert_reg_to_slot a + 7 , "message.return_value" , :message , 5
assert_branch a + 8 , "return_label"
assert_label a + 9 , "return_label"
assert_transfer a + 5 , :"message.data_1" , :message
assert_syscall a + 6 , :exit
assert_slot_to_reg a + 7 ,:message , 5 , "message.return_value"
assert_reg_to_slot a + 8 , "message.return_value" , :message , 5
assert_branch a + 9 , "return_label"
assert_label a + 10 , "return_label"
end
def test_return
assert_return(30)
assert_return(31)
end
end
end

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@ -27,11 +27,11 @@ module SlotMachine
assert_equal Risc::ByteToReg , risc(25).class
assert_equal :"message.receiver" , risc(25).array.symbol
assert_equal :"message.receiver" , risc(25).register.symbol
assert_equal :"integer_1" , risc(25).register.symbol
assert_equal :"message.arg1.data_1" , risc(25).index.symbol
assert_reg_to_slot 26 , "message.receiver" , "id_factory_.next_object" , 2
assert_reg_to_slot 26 , "integer_1" , "id_factory_.next_object" , 2
assert_reg_to_slot 27 , "id_factory_.next_object" , :message , 5
assert_slot_to_reg 28 ,:message , 5 , "message.return_value"
assert_reg_to_slot 29 , "message.return_value" , :message , 5