Commit Graph

1754 Commits

Author SHA1 Message Date
8fa00d1413 move math code to arm
with more bugs surfacing
2020-03-28 12:25:53 +02:00
e51cd8420b move conditional test to arm 2020-03-28 11:51:16 +02:00
2b467fc555 make class method tests arm tests 2020-03-28 09:36:16 +02:00
06944142d6 moving more tests to arm
and guess what, finding bugs (index ones)
not fixed though
2020-03-27 20:18:14 +02:00
c29bb44159 move more tests from interpreter to mains
while now
all interpreter tests with only return tests move now
2020-03-27 19:04:10 +02:00
249e643823 change env name, travis is having trouble 2020-03-26 21:07:01 +02:00
22727ba150 arm tests back on line 2020-03-26 20:30:47 +02:00
94e4f3a9bf better framework for running arm test
more explicit, rather than gobbling files, pass code in
preload is available (so code does not have to be duplicated)
interpret first, so bad mistakes get caught
no ssh, just qemu-arm, configure through env
2020-03-26 20:28:59 +02:00
4bae5c418b fix register use in putstring
was off by one, the syscall is write 
and the first arg is file_descriptor
ie 1 == stdout
2020-03-26 11:24:56 +02:00
bc558d1f0d do not copy name of method
so that the resolve can compare name identity
which is what is does, not equality
this (and some other bug) is crashing arm currently
2020-03-25 12:43:57 +02:00
6d2ecf7ee6 disable arm mains tests until debugged 2020-03-22 18:18:07 +02:00
1970a3ee6e test that register allocation allocates risc names 2020-03-22 18:01:51 +02:00
bc60f02f66 remove risc tests from rubyx layer
duplication, better ones in slot
2020-03-22 17:47:31 +02:00
90935bfbbc risc is GREEN
totally, man.
Small fix in method missing fixed last block tests
(why, i do not know)
2020-03-22 15:58:19 +02:00
37feba1239 bunch of side effects fixed
makes one think if those are valid asserts
2020-03-22 15:56:57 +02:00
ddd1f4e296 fix interpreter syscall and rename return reg
returned int for puts was same name as implicit return  int
2020-03-22 14:31:43 +02:00
be684c0c43 move message to stack_pointer
changing a bunch of register names
some of which get names now
2020-03-22 14:31:43 +02:00
a93a3c8af5 fix most interpreter tests 2020-03-22 14:31:43 +02:00
06ade75593 Fix non ssa issue
register instances were being shared across instructions
causing the setting to have side-effects
Fixed this by copying the register on write
(fixing the symptom rather than the cause, i'll make an issue)
2020-03-22 14:31:43 +02:00
d2e7c647d0 setting registers in the allocator
unfortunately the reg instances are spread across instructions
this causes problems when setting them
2020-03-22 14:31:43 +02:00
c890e8402b change in register_names protocol
move to returning the attribute names
getting and setting can then be automated in the base class
2020-03-22 14:31:43 +02:00
0137056b89 change platform to return register names
not just the number of them
also adds protocol to map registers
(like message to r0 , or syscalls)
2020-03-22 14:31:43 +02:00
f13e6dcf57 fix releasing in allocator
fell into hash new trap, which reuses the object you give it. not good for mutable objects like the array.
also previous logic was broken in terms of machine vs ssa names
2020-03-22 14:31:43 +02:00
3f131a4018 start with register assigning
have to find a way to set them next
2020-03-22 14:31:43 +02:00
4f290ee246 basic liveliness for allocator 2020-03-22 14:31:43 +02:00
8df1b8126f add register names to allocator
make platform instantiate it
basic plumbing
2020-03-22 14:31:43 +02:00
500df01425 rename allocator to standard_allocator
planning to have platform dish it out
2020-03-22 14:31:43 +02:00
2e109a16dc starting on risc allocation
inserting allocator stage in method translation
2020-03-22 14:31:43 +02:00
d5411c7727 Last risc fixes that are not binary, move binary tests
move test that translate or create binary to own directory, 
for semantic distance (they are the only ones still failing)
2020-03-22 14:31:43 +02:00
fea98979e8 Fix comparison bug
Unchanged high level test, ohh how great is testing
2020-03-22 14:31:43 +02:00
f03f445652 passing values to macros
conceptually still a bit open, leaving the hack in for now
passing values to the macro instead of sol instances
2020-03-22 14:31:43 +02:00
e4a79aac50 reset flags in interpreter
fix at least part of the problem why comparisons dont work
2020-03-22 14:31:43 +02:00
0ed5e74748 Fixing ripples from previous 2020-03-22 14:31:43 +02:00
3ce6ed5263 fix putstring and puts
using syscall regs
2020-03-22 14:31:43 +02:00
17a7f29b0c define and use syscall_XX registers
rather than use hardcoded r0 etc use syscall_X
change the syscalls and interpreter to use them
later use platform to map from syscall_X to actually used register (like r0 in arm)
2020-03-22 14:31:43 +02:00
3b50fee158 fix stray misc in slot 2020-03-22 14:31:43 +02:00
9f609bdb06 fix mod and tests 2020-03-22 14:31:43 +02:00
3a983b4fc8 fix plus, which inherited bugs from operator 2020-03-22 14:31:43 +02:00
7232c28ecd operator also fell into ssa trap
relying on register identity
in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue
better now
2020-03-22 14:31:43 +02:00
3145547315 init fell into the ssa tap, fixed
reducing and assuming the same register, buuh
adds a transfer instruction that can hopefully be removed by analysis
2020-03-22 14:31:43 +02:00
5b0c1195e4 Fix interpreter and resolve method
Interpreter was not handling ssa correctly (ie overwriting)
Resolve was assuming wrong registers (also non ssa)
return value still broken
2020-03-22 14:31:43 +02:00
4db71c1c03 fix all uses of operators now they are ssa 2020-03-22 14:31:43 +02:00
61fc8a3991 make operator_instruction single ass
create result register automatically
usually not used, but register allocation will sort that
2020-03-22 14:31:43 +02:00
1378745907 first interpreter tests 2020-03-22 14:31:43 +02:00
c16ed5ab3a fix interpreter
by currently not checking for old register pattern
feels like wip, but passes (all but one)
2020-03-22 14:31:43 +02:00
f2250bc206 fix resolve and introduce method to chop strings to max
strings are 20 bytes. I want to implement the extension idea, just not now
2020-03-22 14:31:43 +02:00
407ca6ef72 misc test fixes 2020-03-22 14:31:43 +02:00
126466e9a9 fixing tests 2020-03-22 14:31:43 +02:00
504fc3509e fix set_internal_word register 2020-03-22 14:31:43 +02:00
5c13ea1433 fix naming mistakes fo Word.get/set macros 2020-03-22 14:31:43 +02:00