bunch of side effects fixed

makes one think if those are valid asserts
This commit is contained in:
Torsten 2020-03-22 15:56:57 +02:00
parent ddd1f4e296
commit 37feba1239
5 changed files with 6 additions and 6 deletions

View File

@ -59,7 +59,7 @@ module SlotMachine
next_method = callable_method[:next_callable].to_reg
callable_method << next_method
branch while_start_label
add_code exit_label

View File

@ -24,7 +24,7 @@ module Risc
assert_equal 0 , Position.get(@linker.cpu_init).at
end
def test_cpu_at
assert_equal "0x8d7c" , Position.get(@linker.cpu_init.first).to_s
assert_equal "0x8d5c" , Position.get(@linker.cpu_init.first).to_s
end
def test_cpu_label
assert_equal Position , Position.get(@linker.cpu_init.first).class

View File

@ -35,7 +35,7 @@ module Risc
ret = main_ticks(46)
assert_equal FunctionReturn , ret.class
assert_equal :r0 , ret.register.symbol
assert_equal 36540 , @interpreter.get_register(ret.register).value
assert_equal 36508 , @interpreter.get_register(ret.register).value
end
end
end

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@ -38,7 +38,7 @@ module Risc
end
def len
1426
1425
end
def test_collect_all_types
@ -70,7 +70,7 @@ module Risc
end
def len
2906
2905
end
end
end

View File

@ -58,7 +58,7 @@ module Risc
end
def test_pc
@interpreter.tick
assert_equal t = 36104 , @interpreter.pc
assert_equal t = 36072 , @interpreter.pc
@interpreter.tick
assert_equal t + 4 , @interpreter.pc
end