3c00239f36
another million index fixes
2018-05-14 15:17:04 +03:00
4a88f342d3
random checkin
...
still suffering -1 trauma
2018-05-14 12:38:44 +03:00
ce3cc72f9e
move all position setting into position
...
Position and subclasses handle the logic, external to
the classes, so it can be swapped out later
(at runtime positions can’t change)
2018-05-07 22:30:43 +03:00
68fb9b1bdc
rename Position get/set
2018-05-06 20:04:02 +03:00
e89c4d1ce1
pass binary that arm instruction belongs to in
...
at least to first. repositioning and stuff next
2018-05-06 19:56:36 +03:00
d65a982454
start by moving positioned(module) to position(class)
2018-05-05 19:47:18 +03:00
43d5521cfc
debugging positions
2018-05-05 19:32:01 +03:00
9e21719aeb
generalise the operator handling
...
ie passing them through
implementing more
2018-04-19 22:13:52 +03:00
f09086e524
unite the two resolve_to_index functions
2018-04-05 20:10:00 +03:00
5bb3ad03cc
some more safety tests
2018-04-05 12:22:40 +03:00
65d57c8c7c
removing unconditional
...
just Branch is fine
2018-04-02 19:30:34 +03:00
6e941ebcb7
introduce load_data instruction
...
which just loads data to a register (used internally)
as opposed to integers, which are objects
2018-03-31 12:38:30 +03:00
1956f18faa
add an integer plus
...
not correctly handling integer objects yet
2018-03-30 17:09:02 +03:00
4253d7a6b9
move assembly from assembler to machine
...
id now called position
2018-03-27 18:47:39 +03:00
4cc1d8455e
fix util namespace
...
and instruction move ripples
2018-03-26 20:05:30 +03:00
e61ef93943
cleanup
2018-03-26 19:17:30 +03:00
b24b65520d
remove all that label stuff
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left over after rewrite from blocks to linked list
2018-03-26 14:54:41 +03:00
231025389a
little cleanup
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code climate inspired
2018-03-26 14:15:48 +03:00
279fdcc1e2
really translate risc - cpu/arm
...
also labels.
Actual translation/assembly is much cleaner
2018-03-25 19:38:59 +03:00
de7e02b0b8
remove IsSame branch from risc
...
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
6a538624c5
remove NotSame from risc
...
instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
9932d0bf33
add source to the to_s
2018-03-22 18:38:19 +02:00
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
b5ef929c9c
add method to risc function call
...
just so we still know at compile time
2018-03-21 19:05:53 +05:30
fcbdba4804
simplify method entry exit codes
...
Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
61a801b00c
Return to_risc
...
remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
fa797f722d
to_risc for NotSameCheck
...
which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
d98e55907e
first go at translating DynamicCall to risc
2018-03-21 11:51:10 +05:30
77084dc894
fix unconditional jump
...
and affected tests
2018-03-20 22:05:09 +05:30
c8980595a3
start to test if
...
truth check is only half done
2018-03-19 21:20:11 +05:30
cddc25a595
fixing tests for shifting constants into slots
2018-03-17 21:15:38 +05:30
79b4b07ac4
style
2018-03-14 17:39:49 +05:30
aa79e41d1c
rename register to risc
...
seems to fit the layer much better as we really have a very reduced
instruction set
2017-01-19 09:02:29 +02:00
