remove IsSame branch from risc
mixing up levels, IsSame is Mom at risc this is a minus and Zero check fix all tests
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@ -19,10 +19,13 @@ module Mom
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left = @condition.to_register(compiler,self)
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false_load = SlotDefinition.new( FalseConstant.new , [] ).to_register(compiler,self)
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left << false_load
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left << Risc::IsSame.new(self , left.register , false_load.register , false_label)
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left << Risc.op( self , :- , left.register , false_load.register)
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left << Risc::IsNotZero.new( self, false_label)
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nil_load = SlotDefinition.new( NilConstant.new , [] ).to_register(compiler,self)
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left << nil_load
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left << Risc::IsSame.new(self , left.register , nil_load.register , false_label)
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left << Risc.op( self , :- , left.register , nil_load.register)
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left << Risc::IsNotZero.new( self, false_label)
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left
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end
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@ -67,14 +67,6 @@ module Risc
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attr_reader :register
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end
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# branch if two registers contain same value
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class IsSame < Branch
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attr_reader :left , :right
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def initialize(source , left , right , label)
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super(source , label)
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end
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end
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class Unconditional < Branch
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end
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@ -7,9 +7,10 @@ module Risc
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def setup
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super
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@input = "if(@a) ; arg = 5 ; else; arg = 6; end"
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@expect = [SlotToReg, SlotToReg, LoadConstant, IsSame, LoadConstant, IsSame ,
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Label, LoadConstant, SlotToReg, RegToSlot, Unconditional, Label ,
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LoadConstant, SlotToReg, RegToSlot, Label]
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero ,
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LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant ,
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SlotToReg, RegToSlot, Unconditional, Label, LoadConstant ,
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SlotToReg, RegToSlot, Label]
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end
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def test_if_instructions
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@ -22,30 +23,30 @@ module Risc
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end
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def test_false_check
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produced = produce_body
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assert_equal produced.next(11) , produced.next(3).label
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assert_equal produced.next(13) , produced.next(4).label
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end
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def test_nil_load
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produced = produce_body
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assert_equal Mom::NilConstant , produced.next(4).constant.class
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assert_equal Mom::NilConstant , produced.next(5).constant.class
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end
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def test_nil_check
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produced = produce_body
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assert_equal produced.next(11) , produced.next(5).label
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assert_equal produced.next(13) , produced.next(7).label
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end
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def test_true_label
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produced = produce_body
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assert produced.next(6).name.start_with?("true_label")
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assert produced.next(8).name.start_with?("true_label")
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end
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def test_merge_label
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produced = produce_body
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assert produced.next(15).name.start_with?("merge_label")
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assert produced.next(17).name.start_with?("merge_label")
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end
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def test_true_jump # should jumpp to merge label
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produced = produce_body
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assert produced.next(10).label.name.start_with?("merge_label")
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assert produced.next(12).label.name.start_with?("merge_label")
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end
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end
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end
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@ -7,8 +7,9 @@ module Risc
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def setup
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super
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@input = "if(@a) ; arg = 5 ; end"
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@expect = [SlotToReg, SlotToReg, LoadConstant, IsSame, LoadConstant, IsSame ,
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Label, LoadConstant, SlotToReg, RegToSlot, Label]
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero ,
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LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant ,
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SlotToReg, RegToSlot, Label]
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end
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def test_if_instructions
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@ -19,22 +20,31 @@ module Risc
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produced = produce_body
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assert_equal Mom::FalseConstant , produced.next(2).constant.class
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end
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def test_isnotzero
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produced = produce_body
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assert_equal IsNotZero , produced.next(4).class
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assert produced.next(4).label.name.start_with?("false_label")
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end
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def test_false_label
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produced = produce_body
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assert_equal Label , produced.next(12).class
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end
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def test_false_check
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produced = produce_body
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assert_equal produced.next(10) , produced.next(3).label
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assert_equal produced.next(12) , produced.next(4).label
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end
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def test_nil_load
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produced = produce_body
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assert_equal Mom::NilConstant , produced.next(4).constant.class
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assert_equal Mom::NilConstant , produced.next(5).constant.class
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end
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def test_nil_check
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produced = produce_body
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assert_equal produced.next(10) , produced.next(5).label
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assert_equal Label , produced.next(4).label.class
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assert_equal produced.next(12) , produced.next(4).label
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end
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def test_true_label
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produced = produce_body
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assert produced.next(6).name.start_with?("true_label")
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assert produced.next(8).name.start_with?("true_label")
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end
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end
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@ -7,8 +7,9 @@ module Risc
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def setup
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super
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@input = "while(@a) ; arg = 5 end"
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, IsSame, LoadConstant ,
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IsSame, LoadConstant, SlotToReg, RegToSlot, Unconditional, Label]
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction ,
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IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant ,
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SlotToReg, RegToSlot, Unconditional, Label]
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end
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def test_while_instructions
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@ -21,25 +22,25 @@ module Risc
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end
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def test_false_check
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produced = produce_body
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assert_equal produced.next(11) , produced.next(4).label
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assert_equal produced.next(13) , produced.next(5).label
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end
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def test_nil_load
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produced = produce_body
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assert_equal Mom::NilConstant , produced.next(5).constant.class
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assert_equal Mom::NilConstant , produced.next(6).constant.class
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end
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def test_nil_check
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produced = produce_body
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assert_equal produced.next(11) , produced.next(6).label
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assert_equal produced.next(13) , produced.next(8).label
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end
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def test_merge_label
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produced = produce_body
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assert produced.next(11).name.start_with?("merge_label")
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assert produced.next(13).name.start_with?("merge_label")
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end
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def test_back_jump # should jump back to condition label
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produced = produce_body
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assert_equal produced , produced.next(10).label
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assert_equal produced , produced.next(12).label
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end
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end
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end
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