Commit Graph

2728 Commits

Author SHA1 Message Date
3a3a9277b3 fix operators registers 2020-03-22 14:31:43 +02:00
8867d60c13 fix method_missing register
logic is still wrong, even it is slightly less (at least loading the method name)
2020-03-22 14:31:43 +02:00
ede103e73d finally did assert_function_call
for cleaner reading, like all other instruction asserts
2020-03-22 14:31:43 +02:00
cf5a3c0102 fix inits registers
surprisingly easy. shorter code and more readable tests
2020-03-22 14:31:43 +02:00
7d8ef8ef64 fix allocate tests
as allocate got one smaller
2020-03-22 14:31:43 +02:00
8abcaa330b fix allocate in builder
which accessed unknown types.
also moved assert_allocate to support
2020-03-22 14:31:43 +02:00
c9fedec230 add a way to bend the type for register_value
specifically for factories, where we know the type of next_object even it is not specified
2020-03-22 14:31:43 +02:00
8119030ed2 fix return sequence
broken due to logic error in register_slot << (which was reducing the wrong register, self, not the arg)

Still the sequence is in 2 places, one too many ?
2020-03-22 14:31:43 +02:00
05ddc70fd6 fix get_internal word register names
seems previous commits broke the return
2020-03-22 14:31:43 +02:00
6267bf3ad0 fix slot_to_reg to allow register indexes
we mostly use pre-calculated indexes, ie integers
but registers are allowed (in arm/risc), so we try to check the registers type at least is right.
The return is really a machine word, but we call it Object (yes, more work that way)
2020-03-22 14:31:43 +02:00
62d8d92b50 restrict list index to integer 2020-03-22 14:31:43 +02:00
a70e510548 fix test_exit registers 2020-03-22 14:31:43 +02:00
fb4fa598f2 fix get_internal_byte
improved operators and tests
some logic errors still
2020-03-22 14:31:43 +02:00
a70f63e7bb fix remaining slot instruction tests 2020-03-22 14:31:43 +02:00
07873ce068 fix not same logic
caused by assert logic error, also fixed
2020-03-22 14:31:43 +02:00
c1cfc12a1c converted resolve_method
Big, left till last, but surprisingly painless
2020-03-22 14:31:43 +02:00
12fe0b9a10 add constants automatically 2020-03-22 14:31:43 +02:00
28e9cd335a still fixing instruction tests 2020-03-22 14:31:43 +02:00
e6729b8b60 fixing instruction tests 2020-03-22 14:31:43 +02:00
22d513d895 fix div4 and tests
also bug in reduce_int, compiler not carried through
2020-03-22 14:31:43 +02:00
eed9ba082f Fix div10 and test
fix and use load_data (similar to load_constant)
and integrate into load_object when appropriate (ie for integers)
2020-03-22 14:31:43 +02:00
bd02f69824 reduce_int was overwriting register
No more. But the type question is open, ie what type does the resulting register have
2020-03-22 14:31:43 +02:00
53eb28fff4 load constant to create register names with class
Just the id_ did give no clue to the contents, just took care of the uniqueness.
Better for debugging
2020-03-22 14:31:43 +02:00
3ec5557ddb fix builder logic error
and tests
2020-03-22 14:31:43 +02:00
1760b5b203 fix comparison test and helpers
moving to passing the instruction number, not the instruction
so in the error message we can say where the error is
(otherwise minitest is good enough to supress the trace of asserts calling asserts)
2020-03-22 14:31:43 +02:00
3575aada17 tests for all macros
generated on master (know to work)
but with rXX registers, needs fixing
2020-03-22 14:31:43 +02:00
9c5d17a3bb Fix div10 without method_missing
but reanimate infer_type to auto create the needed regsiters
also some helpers
2020-03-22 14:31:43 +02:00
9a5e0f15cd reannimate infer_type
now with a _purpose_
2020-03-22 14:31:43 +02:00
3688c967d3 Fix comparison macro
which leaves a definite need for instruction level testing
2020-03-22 14:31:43 +02:00
2af953e1d2 last instruciton, dynamic_call
next macros
2020-03-22 14:31:43 +02:00
7f5ebab800 did block yield 2020-03-22 14:31:43 +02:00
a4c0b8e5f9 did return sequence
surprisingly easy. also some check polish
2020-03-22 14:31:43 +02:00
fd43fc9e5c finally fixes the builder 2020-03-22 14:31:43 +02:00
db5a59f735 Unify instruction namings also dirs
Was getting confused myself, where it was instruction or instructions, when if the base class was inside or out of dir.
Now dirs are plural, and base class is inside.
2020-03-22 14:31:43 +02:00
f3d299208e fix message_setup with new builder 2020-03-22 14:31:43 +02:00
d0036ed95b better way to test object registers
also some cleaning, by using more helpers
2020-03-22 14:31:43 +02:00
ece1e8c87b fix some more of builder
but still not all. removed some and fixed the register allocation in allocate_int
2020-03-22 14:31:43 +02:00
ff49ff50c0 Convert SimpleCall to new regs
Also fix bug in RegsiterValue/Slot with chain, where logic was dodgy and compiler not set
2020-03-22 14:31:43 +02:00
4b303977a7 Fix first Slot instruction that uses builder
now without method_missing and names
but still with instance_eval, hmm. Tried without, makes code much less readable
2020-03-22 14:31:43 +02:00
4888b3b6db Starting to rework slot instructions that create risc
have to go through all and all macros and all thems tests. What did the wise man say: one step at a time
2020-03-22 14:31:43 +02:00
4643be0ae6 codong RegisterSlot with reg and slot 2020-03-22 14:31:43 +02:00
64d860b2bf create a load on the compiler
thus removing the need for << with objects on RegisterValue
2020-03-22 14:31:43 +02:00
95f3eec043 repurpose RValue as RegisterSlot
with the idea of the better name came also the one about not needing the builder anymore
2020-03-22 14:31:43 +02:00
088017bc05 SA for Slotted derivations
Object and Constant similarity are coming more into focus. Will unite after the merge
2020-03-22 14:31:43 +02:00
d22da1ab97 SA for slot_to_reg 2020-03-22 14:31:43 +02:00
77003eed06 remove use_reg on compiler and SA for load 2020-03-22 14:31:43 +02:00
0ce14bdfd1 moving to SA register names (wip)
starting to implement register allocation by first creating SA
Single Assignment means a register is only every assigned a value once. Hence for any operation involving another register, a new register is created.
We do this with a naming scheme for the registers in dot notation (as it would be in c) which means 2 registers with the same name, should have the same contents. This does not apply to temporaries, but that is another day.
Starting WIP now, and will create many red commits before merging when green.
2020-03-22 14:31:43 +02:00
f2c853821c First version of BeginnersGuide and other doc changes 2020-03-21 19:02:02 +02:00
a40d8f2e8c update ffi for 2.7 2020-03-21 12:41:56 +02:00
887d7b9bbb replace fake compiler with real
less room for error
2020-02-28 12:54:17 +02:00