3145547315
init fell into the ssa tap, fixed
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reducing and assuming the same register, buuh
adds a transfer instruction that can hopefully be removed by analysis
2020-03-22 14:31:43 +02:00
5b0c1195e4
Fix interpreter and resolve method
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Interpreter was not handling ssa correctly (ie overwriting)
Resolve was assuming wrong registers (also non ssa)
return value still broken
2020-03-22 14:31:43 +02:00
4db71c1c03
fix all uses of operators now they are ssa
2020-03-22 14:31:43 +02:00
0cde7c1d0a
debugging to find operator not being ssa
2020-03-22 14:31:43 +02:00
61fc8a3991
make operator_instruction single ass
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create result register automatically
usually not used, but register allocation will sort that
2020-03-22 14:31:43 +02:00
1378745907
first interpreter tests
2020-03-22 14:31:43 +02:00
c16ed5ab3a
fix interpreter
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by currently not checking for old register pattern
feels like wip, but passes (all but one)
2020-03-22 14:31:43 +02:00
f2250bc206
fix resolve and introduce method to chop strings to max
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strings are 20 bytes. I want to implement the extension idea, just not now
2020-03-22 14:31:43 +02:00
504fc3509e
fix set_internal_word register
2020-03-22 14:31:43 +02:00
5c13ea1433
fix naming mistakes fo Word.get/set macros
2020-03-22 14:31:43 +02:00
d125a1528a
Fix set_internal_byte registers
2020-03-22 14:31:43 +02:00
2656bfacb2
create a reduce_int on RegisterSlot
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that just passes through to RegisterValue by calling to_reg
2020-03-22 14:31:43 +02:00
17a1121408
fix putstring registers
2020-03-22 14:31:43 +02:00
3a3a9277b3
fix operators registers
2020-03-22 14:31:43 +02:00
8867d60c13
fix method_missing register
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logic is still wrong, even it is slightly less (at least loading the method name)
2020-03-22 14:31:43 +02:00
cf5a3c0102
fix inits registers
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surprisingly easy. shorter code and more readable tests
2020-03-22 14:31:43 +02:00
8abcaa330b
fix allocate in builder
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which accessed unknown types.
also moved assert_allocate to support
2020-03-22 14:31:43 +02:00
c9fedec230
add a way to bend the type for register_value
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specifically for factories, where we know the type of next_object even it is not specified
2020-03-22 14:31:43 +02:00
05ddc70fd6
fix get_internal word register names
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seems previous commits broke the return
2020-03-22 14:31:43 +02:00
6267bf3ad0
fix slot_to_reg to allow register indexes
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we mostly use pre-calculated indexes, ie integers
but registers are allowed (in arm/risc), so we try to check the registers type at least is right.
The return is really a machine word, but we call it Object (yes, more work that way)
2020-03-22 14:31:43 +02:00
62d8d92b50
restrict list index to integer
2020-03-22 14:31:43 +02:00
a70e510548
fix test_exit registers
2020-03-22 14:31:43 +02:00
fb4fa598f2
fix get_internal_byte
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improved operators and tests
some logic errors still
2020-03-22 14:31:43 +02:00
c1cfc12a1c
converted resolve_method
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Big, left till last, but surprisingly painless
2020-03-22 14:31:43 +02:00
12fe0b9a10
add constants automatically
2020-03-22 14:31:43 +02:00
e6729b8b60
fixing instruction tests
2020-03-22 14:31:43 +02:00
22d513d895
fix div4 and tests
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also bug in reduce_int, compiler not carried through
2020-03-22 14:31:43 +02:00
eed9ba082f
Fix div10 and test
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fix and use load_data (similar to load_constant)
and integrate into load_object when appropriate (ie for integers)
2020-03-22 14:31:43 +02:00
bd02f69824
reduce_int was overwriting register
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No more. But the type question is open, ie what type does the resulting register have
2020-03-22 14:31:43 +02:00
53eb28fff4
load constant to create register names with class
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Just the id_ did give no clue to the contents, just took care of the uniqueness.
Better for debugging
2020-03-22 14:31:43 +02:00
3ec5557ddb
fix builder logic error
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and tests
2020-03-22 14:31:43 +02:00
1760b5b203
fix comparison test and helpers
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moving to passing the instruction number, not the instruction
so in the error message we can say where the error is
(otherwise minitest is good enough to supress the trace of asserts calling asserts)
2020-03-22 14:31:43 +02:00
9c5d17a3bb
Fix div10 without method_missing
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but reanimate infer_type to auto create the needed regsiters
also some helpers
2020-03-22 14:31:43 +02:00
9a5e0f15cd
reannimate infer_type
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now with a _purpose_
2020-03-22 14:31:43 +02:00
3688c967d3
Fix comparison macro
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which leaves a definite need for instruction level testing
2020-03-22 14:31:43 +02:00
2af953e1d2
last instruciton, dynamic_call
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next macros
2020-03-22 14:31:43 +02:00
7f5ebab800
did block yield
2020-03-22 14:31:43 +02:00
a4c0b8e5f9
did return sequence
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surprisingly easy. also some check polish
2020-03-22 14:31:43 +02:00
fd43fc9e5c
finally fixes the builder
2020-03-22 14:31:43 +02:00
db5a59f735
Unify instruction namings also dirs
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Was getting confused myself, where it was instruction or instructions, when if the base class was inside or out of dir.
Now dirs are plural, and base class is inside.
2020-03-22 14:31:43 +02:00
f3d299208e
fix message_setup with new builder
2020-03-22 14:31:43 +02:00
ece1e8c87b
fix some more of builder
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but still not all. removed some and fixed the register allocation in allocate_int
2020-03-22 14:31:43 +02:00
ff49ff50c0
Convert SimpleCall to new regs
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Also fix bug in RegsiterValue/Slot with chain, where logic was dodgy and compiler not set
2020-03-22 14:31:43 +02:00
4b303977a7
Fix first Slot instruction that uses builder
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now without method_missing and names
but still with instance_eval, hmm. Tried without, makes code much less readable
2020-03-22 14:31:43 +02:00
4888b3b6db
Starting to rework slot instructions that create risc
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have to go through all and all macros and all thems tests. What did the wise man say: one step at a time
2020-03-22 14:31:43 +02:00
4643be0ae6
codong RegisterSlot with reg and slot
2020-03-22 14:31:43 +02:00
64d860b2bf
create a load on the compiler
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thus removing the need for << with objects on RegisterValue
2020-03-22 14:31:43 +02:00
95f3eec043
repurpose RValue as RegisterSlot
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with the idea of the better name came also the one about not needing the builder anymore
2020-03-22 14:31:43 +02:00
088017bc05
SA for Slotted derivations
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Object and Constant similarity are coming more into focus. Will unite after the merge
2020-03-22 14:31:43 +02:00
d22da1ab97
SA for slot_to_reg
2020-03-22 14:31:43 +02:00
