0137056b89
change platform to return register names
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not just the number of them
also adds protocol to map registers
(like message to r0 , or syscalls)
2020-03-22 14:31:43 +02:00
f13e6dcf57
fix releasing in allocator
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fell into hash new trap, which reuses the object you give it. not good for mutable objects like the array.
also previous logic was broken in terms of machine vs ssa names
2020-03-22 14:31:43 +02:00
3f131a4018
start with register assigning
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have to find a way to set them next
2020-03-22 14:31:43 +02:00
4f290ee246
basic liveliness for allocator
2020-03-22 14:31:43 +02:00
8df1b8126f
add register names to allocator
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make platform instantiate it
basic plumbing
2020-03-22 14:31:43 +02:00
500df01425
rename allocator to standard_allocator
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planning to have platform dish it out
2020-03-22 14:31:43 +02:00
2e109a16dc
starting on risc allocation
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inserting allocator stage in method translation
2020-03-22 14:31:43 +02:00
d5411c7727
Last risc fixes that are not binary, move binary tests
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move test that translate or create binary to own directory,
for semantic distance (they are the only ones still failing)
2020-03-22 14:31:43 +02:00
fea98979e8
Fix comparison bug
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Unchanged high level test, ohh how great is testing
2020-03-22 14:31:43 +02:00
0ed5e74748
Fixing ripples from previous
2020-03-22 14:31:43 +02:00
3ce6ed5263
fix putstring and puts
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using syscall regs
2020-03-22 14:31:43 +02:00
3b50fee158
fix stray misc in slot
2020-03-22 14:31:43 +02:00
9f609bdb06
fix mod and tests
2020-03-22 14:31:43 +02:00
3a983b4fc8
fix plus, which inherited bugs from operator
2020-03-22 14:31:43 +02:00
7232c28ecd
operator also fell into ssa trap
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relying on register identity
in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue
better now
2020-03-22 14:31:43 +02:00
3145547315
init fell into the ssa tap, fixed
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reducing and assuming the same register, buuh
adds a transfer instruction that can hopefully be removed by analysis
2020-03-22 14:31:43 +02:00
5b0c1195e4
Fix interpreter and resolve method
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Interpreter was not handling ssa correctly (ie overwriting)
Resolve was assuming wrong registers (also non ssa)
return value still broken
2020-03-22 14:31:43 +02:00
4db71c1c03
fix all uses of operators now they are ssa
2020-03-22 14:31:43 +02:00
61fc8a3991
make operator_instruction single ass
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create result register automatically
usually not used, but register allocation will sort that
2020-03-22 14:31:43 +02:00
1378745907
first interpreter tests
2020-03-22 14:31:43 +02:00
c16ed5ab3a
fix interpreter
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by currently not checking for old register pattern
feels like wip, but passes (all but one)
2020-03-22 14:31:43 +02:00
407ca6ef72
misc test fixes
2020-03-22 14:31:43 +02:00
8abcaa330b
fix allocate in builder
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which accessed unknown types.
also moved assert_allocate to support
2020-03-22 14:31:43 +02:00
c9fedec230
add a way to bend the type for register_value
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specifically for factories, where we know the type of next_object even it is not specified
2020-03-22 14:31:43 +02:00
6267bf3ad0
fix slot_to_reg to allow register indexes
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we mostly use pre-calculated indexes, ie integers
but registers are allowed (in arm/risc), so we try to check the registers type at least is right.
The return is really a machine word, but we call it Object (yes, more work that way)
2020-03-22 14:31:43 +02:00
fb4fa598f2
fix get_internal_byte
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improved operators and tests
some logic errors still
2020-03-22 14:31:43 +02:00
22d513d895
fix div4 and tests
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also bug in reduce_int, compiler not carried through
2020-03-22 14:31:43 +02:00
eed9ba082f
Fix div10 and test
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fix and use load_data (similar to load_constant)
and integrate into load_object when appropriate (ie for integers)
2020-03-22 14:31:43 +02:00
bd02f69824
reduce_int was overwriting register
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No more. But the type question is open, ie what type does the resulting register have
2020-03-22 14:31:43 +02:00
53eb28fff4
load constant to create register names with class
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Just the id_ did give no clue to the contents, just took care of the uniqueness.
Better for debugging
2020-03-22 14:31:43 +02:00
9c5d17a3bb
Fix div10 without method_missing
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but reanimate infer_type to auto create the needed regsiters
also some helpers
2020-03-22 14:31:43 +02:00
9a5e0f15cd
reannimate infer_type
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now with a _purpose_
2020-03-22 14:31:43 +02:00
3688c967d3
Fix comparison macro
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which leaves a definite need for instruction level testing
2020-03-22 14:31:43 +02:00
fd43fc9e5c
finally fixes the builder
2020-03-22 14:31:43 +02:00
db5a59f735
Unify instruction namings also dirs
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Was getting confused myself, where it was instruction or instructions, when if the base class was inside or out of dir.
Now dirs are plural, and base class is inside.
2020-03-22 14:31:43 +02:00
d0036ed95b
better way to test object registers
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also some cleaning, by using more helpers
2020-03-22 14:31:43 +02:00
ece1e8c87b
fix some more of builder
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but still not all. removed some and fixed the register allocation in allocate_int
2020-03-22 14:31:43 +02:00
ff49ff50c0
Convert SimpleCall to new regs
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Also fix bug in RegsiterValue/Slot with chain, where logic was dodgy and compiler not set
2020-03-22 14:31:43 +02:00
4888b3b6db
Starting to rework slot instructions that create risc
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have to go through all and all macros and all thems tests. What did the wise man say: one step at a time
2020-03-22 14:31:43 +02:00
4643be0ae6
codong RegisterSlot with reg and slot
2020-03-22 14:31:43 +02:00
64d860b2bf
create a load on the compiler
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thus removing the need for << with objects on RegisterValue
2020-03-22 14:31:43 +02:00
95f3eec043
repurpose RValue as RegisterSlot
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with the idea of the better name came also the one about not needing the builder anymore
2020-03-22 14:31:43 +02:00
d22da1ab97
SA for slot_to_reg
2020-03-22 14:31:43 +02:00
77003eed06
remove use_reg on compiler and SA for load
2020-03-22 14:31:43 +02:00
0ce14bdfd1
moving to SA register names (wip)
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starting to implement register allocation by first creating SA
Single Assignment means a register is only every assigned a value once. Hence for any operation involving another register, a new register is created.
We do this with a naming scheme for the registers in dot notation (as it would be in c) which means 2 registers with the same name, should have the same contents. This does not apply to temporaries, but that is another day.
Starting WIP now, and will create many red commits before merging when green.
2020-03-22 14:31:43 +02:00
887d7b9bbb
replace fake compiler with real
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less room for error
2020-02-28 12:54:17 +02:00
685022a6e0
Externalise register allocation into own class
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On the way to the register allocation
2020-02-27 11:57:18 +02:00
8832df3221
Add number of registers to platform
2020-02-26 19:01:01 +02:00
aa9fc8bc81
More rename cleanp
2019-10-03 21:07:55 +03:00
c43436f35a
Change Mom to SlotMachine
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rather large commit, but essentially a simple rename
Rationale in docs and blogs
2019-10-03 20:55:41 +03:00
