2014-05-03 21:18:04 +02:00
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require_relative "code"
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2014-08-22 16:40:09 +02:00
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module Register
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2014-05-03 14:13:44 +02:00
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2014-08-22 17:00:23 +02:00
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# The register machine model is close to current hardware and has following instruction classes
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2014-05-03 14:13:44 +02:00
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# - Memory
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# - Stack
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# - Logic
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# - Math
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# - Control/Compare
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# - Move
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# - Call
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# Instruction derives from Code, for the assembly api
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2014-05-03 21:18:04 +02:00
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2014-09-16 16:16:56 +02:00
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class Instruction < Virtual::Object
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2014-05-18 09:27:35 +02:00
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def initialize options
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2014-05-05 14:59:29 +02:00
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@attributes = options
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2014-05-03 21:18:04 +02:00
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end
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2014-06-12 12:47:06 +02:00
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attr_reader :attributes
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2014-05-19 10:28:13 +02:00
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def opcode
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@attributes[:opcode]
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end
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2014-06-12 20:04:15 +02:00
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#abstract, only should be called from derived
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def to_s
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atts = @attributes.dup
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atts.delete(:opcode)
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atts.delete(:update_status)
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atts.delete(:condition_code) if atts[:condition_code] == :al
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atts.empty? ? "" : ", #{atts}"
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end
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2014-06-14 09:59:25 +02:00
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# returns an array of registers (RegisterReferences) that this instruction uses.
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2014-06-08 00:41:56 +02:00
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# ie for r1 = r2 + r3
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# which in assembler is add r1 , r2 , r3
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# it would return [r2,r3]
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# for pushes the list may be longer, whereas for a jump empty
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def uses
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raise "abstract called for #{self.class}"
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end
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2014-06-14 09:59:25 +02:00
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# returns an array of registers (RegisterReferences) that this instruction assigns to.
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2014-06-08 00:41:56 +02:00
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# ie for r1 = r2 + r3
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# which in assembler is add r1 , r2 , r3
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# it would return [r1]
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# for most instruction this is one, but comparisons and jumps 0 , and pop's as long as 16
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def assigns
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raise "abstract called for #{self.class}"
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end
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2014-05-21 11:47:40 +02:00
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def method_missing name , *args , &block
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return super unless (args.length <= 1) or block_given?
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set , attribute = name.to_s.split("set_")
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if set == ""
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@attributes[attribute.to_sym] = args[0] || 1
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return self
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else
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return super
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end
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return @attributes[name.to_sym]
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end
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2014-05-02 07:02:25 +02:00
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end
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2014-05-03 14:13:44 +02:00
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class StackInstruction < Instruction
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def initialize first , options = {}
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@first = first
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super(options)
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end
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2014-06-09 18:24:09 +02:00
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# when calling we place a dummy push/pop in the stream and calculate later what registers actually need saving
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def set_registers regs
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@first = regs.collect{ |r| r.symbol }
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end
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2014-06-08 00:41:56 +02:00
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def is_push?
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opcode == :push
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end
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def is_pop?
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!is_push?
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end
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def uses
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is_push? ? regs : []
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end
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def assigns
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is_pop? ? regs : []
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end
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def regs
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@first
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end
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2014-06-12 20:04:15 +02:00
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def to_s
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"#{opcode} [#{@first.collect {|f| f.to_asm}.join(',') }] #{super}"
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2014-06-12 20:04:15 +02:00
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end
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end
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class MemoryInstruction < Instruction
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2014-06-01 20:20:44 +02:00
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def initialize result , left , right = nil , options = {}
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@result = result
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@left = left
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@right = right
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2014-05-18 09:27:35 +02:00
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super(options)
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end
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2014-06-08 00:41:56 +02:00
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def uses
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2014-06-14 10:12:53 +02:00
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ret = [@left.register ]
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ret << @right.register unless @right.nil?
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ret
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end
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def assigns
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[@result.register]
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end
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end
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class LogicInstruction < Instruction
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# result = left op right
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#
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# Logic instruction are your basic operator implementation. But unlike the (normal) code we write
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# these Instructions must have "place" to write their results. Ie when you write 4 + 5 in ruby
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# the result is sort of up in the air, but with Instructions the result must be assigned
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2014-05-19 10:28:13 +02:00
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def initialize result , left , right , options = {}
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2014-05-18 11:18:57 +02:00
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@result = result
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@left = left
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2014-08-30 18:40:37 +02:00
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@right = right.is_a?(Fixnum) ? Virtual::IntegerConstant.new(right) : right
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2014-05-18 09:27:35 +02:00
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super(options)
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end
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2014-06-11 10:41:50 +02:00
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attr_accessor :result , :left , :right
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def uses
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ret = []
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2014-06-14 10:12:53 +02:00
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ret << @left.register if @left and not @left.is_a? Constant
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ret << @right.register if @right and not @right.is_a?(Constant)
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ret
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end
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def assigns
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[@result.register]
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end
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2014-06-17 14:25:33 +02:00
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def to_s
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2014-06-12 20:40:25 +02:00
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"#{opcode} #{result.to_asm} , #{left.to_asm} , #{right.to_asm} #{super}"
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2014-06-12 20:04:15 +02:00
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end
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2014-05-03 14:13:44 +02:00
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end
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class CompareInstruction < Instruction
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def initialize left , right , options = {}
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@left = left
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@right = right.is_a?(Fixnum) ? IntegerConstant.new(right) : right
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super(options)
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end
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2014-06-08 00:41:56 +02:00
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def uses
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2014-06-14 10:12:53 +02:00
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ret = [@left.register ]
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ret << @right.register unless @right.is_a? Constant
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2014-06-08 00:41:56 +02:00
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ret
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end
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def assigns
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[]
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end
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2014-06-17 14:25:33 +02:00
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def to_s
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"#{opcode} #{@left.to_asm} , #{@right.to_asm} #{super}"
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end
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2014-05-03 14:13:44 +02:00
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end
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class MoveInstruction < Instruction
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def initialize to , from , options = {}
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@to = to
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@from = from.is_a?(Fixnum) ? Virtual::IntegerConstant.new(from) : from
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2014-06-07 16:59:44 +02:00
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raise "move must have from set #{inspect}" unless from
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2014-05-18 09:27:35 +02:00
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super(options)
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end
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2014-06-11 10:41:50 +02:00
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attr_accessor :to , :from
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def uses
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@from.is_a?(Constant) ? [] : [@from.register]
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end
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def assigns
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[@to.register]
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end
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2014-06-12 20:04:15 +02:00
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def to_s
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2014-06-12 20:40:25 +02:00
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"#{opcode} #{@to.to_asm} , #{@from.to_asm} #{super}"
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end
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2014-05-03 14:13:44 +02:00
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end
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class CallInstruction < Instruction
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def initialize first , options = {}
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@first = first
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super(options)
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2014-05-14 09:47:30 +02:00
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opcode = @attributes[:opcode].to_s
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if opcode.length == 3 and opcode[0] == "b"
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@attributes[:condition_code] = opcode[1,2].to_sym
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@attributes[:opcode] = :b
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end
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2014-05-15 15:54:23 +02:00
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if opcode.length == 6 and opcode[0] == "c"
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@attributes[:condition_code] = opcode[4,2].to_sym
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@attributes[:opcode] = :call
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end
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2014-05-14 09:47:30 +02:00
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end
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2014-06-08 00:41:56 +02:00
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def uses
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2014-06-12 20:27:30 +02:00
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if opcode == :call
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2014-06-14 10:12:53 +02:00
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@first.args.collect {|arg| arg.register }
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2014-06-12 20:27:30 +02:00
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else
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[]
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end
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2014-06-08 00:41:56 +02:00
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end
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def assigns
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2014-06-12 20:27:30 +02:00
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if opcode == :call
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2014-06-14 09:59:25 +02:00
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[RegisterReference.new(RegisterMachine.instance.return_register)]
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2014-06-12 20:27:30 +02:00
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else
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[]
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end
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2014-06-08 00:41:56 +02:00
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end
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2014-06-17 14:25:33 +02:00
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def to_s
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"#{opcode} #{@first.to_asm} #{super}"
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end
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2014-05-03 14:13:44 +02:00
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end
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2014-05-02 07:02:25 +02:00
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end
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