adjusted module name accordingly

This commit is contained in:
Torsten Ruger
2014-08-22 17:40:09 +03:00
parent b100956909
commit b196810e89
8 changed files with 8 additions and 8 deletions
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module Vm
module Register
# Base class for anything that we can assemble
# Derived classes include instructions and constants(data)
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require_relative "code"
module Vm
module Register
# Because the idea of what one instruction does, does not always map one to one to real machine
# instructions, and instruction may link to another instruction thus creating an arbitrary list
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module Vm
module Register
class Integer < Word
# needs to be here as Word's constructor is private (to make it abstract)
def initialize reg
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module Vm
module Register
class Mystery < Word
# needs to be here as Word's constructor is private (to make it abstract)
def initilize reg
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module Vm
module Register
# Passes, or BlockPasses, could have been procs that just get each block passed.
# Instead they are proper objects in case they want to save state.
# The idea is
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module Vm
module Register
class Reference < Word
# needs to be here as Word's constructor is private (to make it abstract)
def initialize reg , clazz = nil
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module Vm
module Register
# Our virtual c-machine has a number of registers of a given size and uses a stack
# So much so standard
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module Vm
module Register
# RegisterReference is not the name for a register, "only" for a certain use of it.
# In a way it is like a variable name, a storage location. The location is a register off course,