some inlining and renaming

This commit is contained in:
Torsten Ruger 2014-06-14 11:12:53 +03:00
parent 0dbaebf647
commit 87fa71277a
4 changed files with 37 additions and 77 deletions

View File

@ -24,47 +24,6 @@ module Arm
RECEIVER_REG
end
def integer_equals block , left , right
block.add_code cmp( left , right )
Vm::BranchCondition.new :eq
end
def integer_less_or_equal block , left , right
block.add_code cmp( left , right )
Vm::BranchCondition.new :le
end
def integer_greater_or_equal block , left , right
block.add_code cmp( left , right )
Vm::BranchCondition.new :ge
end
def integer_less_than block , left , right
block.add_code cmp( left , right )
Vm::BranchCondition.new :lt
end
def integer_greater_than block , left , right
block.add_code cmp( left , right )
Vm::BranchCondition.new :gt
end
# TODO wrong type, should be object_reference. But that needs the actual typing to work
def integer_at_index block , result ,left , right
block.add_code ldr( result , left , right )
result
end
def integer_plus block , result , left , right
block.add_code add( result , left , right )
result
end
def integer_minus block , result , left , right
block.add_code sub( result , left , right )
result
end
def integer_left_shift block , result , left , right
block.add_code mov( result , left , shift_lsr: right )
result
end
def function_call into , call
raise "Not CallSite #{call.inspect}" unless call.is_a? Vm::CallSite
raise "Not linked #{call.inspect}" unless call.function

View File

@ -43,7 +43,7 @@ module Vm
shouldda = RegisterReference.new(RegisterMachine.instance.receiver_register).next_reg_use(i + 1)
if arg.is_a?(Value)
@args[i] = arg
raise "arg #{i} in non std register #{arg.used_register}, expecting #{shouldda}" unless shouldda == arg.used_register
raise "arg #{i} in non std register #{arg.register}, expecting #{shouldda}" unless shouldda == arg.register
else
@args[i] = arg.new(shouldda)
end

View File

@ -101,12 +101,12 @@ module Vm
super(options)
end
def uses
ret = [@left.used_register ]
ret << @right.used_register unless @right.nil?
ret = [@left.register ]
ret << @right.register unless @right.nil?
ret
end
def assigns
[@result.used_register]
[@result.register]
end
end
class LogicInstruction < Instruction
@ -124,12 +124,12 @@ module Vm
attr_accessor :result , :left , :right
def uses
ret = []
ret << @left.used_register if @left and not @left.is_a? Constant
ret << @right.used_register if @right and not @right.is_a?(Constant)
ret << @left.register if @left and not @left.is_a? Constant
ret << @right.register if @right and not @right.is_a?(Constant)
ret
end
def assigns
[@result.used_register]
[@result.register]
end
def to_asm
"#{opcode} #{result.to_asm} , #{left.to_asm} , #{right.to_asm} #{super}"
@ -142,8 +142,8 @@ module Vm
super(options)
end
def uses
ret = [@left.used_register ]
ret << @right.used_register unless @right.is_a? Constant
ret = [@left.register ]
ret << @right.register unless @right.is_a? Constant
ret
end
def assigns
@ -159,10 +159,10 @@ module Vm
end
attr_accessor :to , :from
def uses
@from.is_a?(Constant) ? [] : [@from.used_register]
@from.is_a?(Constant) ? [] : [@from.register]
end
def assigns
[@to.used_register]
[@to.register]
end
def to_s
"#{opcode} #{@to.to_asm} , #{@from.to_asm} #{super}"
@ -184,7 +184,7 @@ module Vm
end
def uses
if opcode == :call
@first.args.collect {|arg| arg.used_register }
@first.args.collect {|arg| arg.register }
else
[]
end

View File

@ -21,6 +21,7 @@ module Vm
end
# Just a nice way to write branches
# Comparisons produce them, and branches take them as argument.
class BranchCondition < Value
def initialize operator
@ -49,10 +50,10 @@ module Vm
# remembering that our oo machine is typed, no overloading or stuff
class Word < Value
attr_accessor :used_register
attr_accessor :register
def register_symbol
@used_register.symbol
@register.symbol
end
def inspect
"#{self.class.name} (#{register_symbol})"
@ -62,9 +63,9 @@ module Vm
end
def initialize reg
if reg.is_a? RegisterReference
@used_register = reg
@register = reg
else
@used_register = RegisterReference.new(reg)
@register = RegisterReference.new(reg)
end
end
def length
@ -86,40 +87,40 @@ module Vm
class Integer < Word
def less_or_equal block , right
RegisterMachine.instance.integer_less_or_equal block , self , right
block.cmp( self , right )
Vm::BranchCondition.new :le
end
def greater_or_equal block , right
RegisterMachine.instance.integer_greater_or_equal block , self , right
block.cmp( self , right )
Vm::BranchCondition.new :ge
end
def greater_than block , right
RegisterMachine.instance.integer_greater_than block , self , right
block.cmp( self , right )
Vm::BranchCondition.new :gt
end
def less_than block , right
RegisterMachine.instance.integer_less_than block , self , right
block.cmp( self , right )
Vm::BranchCondition.new :lt
end
# def == other
# code = class_for(CompareInstruction).new(self , other , opcode: :cmp)
# end
# def + other
# class_for(LogicInstruction).new(nil , self , other , opcode: :add)
# end
# def - other
# class_for(LogicInstruction).new(nil , self , other , opcode: :sub )#, update_status: 1 )
# end
def at_index block , left , right
RegisterMachine.instance.integer_at_index block , self , left , right
block.ldr( self , left , right )
self
end
def plus block , first , right
RegisterMachine.instance.integer_plus block , self , first , right
block.add( self , left , right )
self
end
def minus block , first , right
RegisterMachine.instance.integer_minus block , self , first , right
def minus block , left , right
block.sub( self , left , right )
self
end
def left_shift block , first , right
RegisterMachine.instance.integer_left_shift block , self , first , right
block.mov( self , left , shift_lsr: right )
self
end
def equals block , right
RegisterMachine.instance.integer_equals block , self , right
block.cmp( self , right )
Vm::BranchCondition.new :eq
end
def load block , right
@ -127,7 +128,7 @@ module Vm
block.mov( self , right ) #move the value
elsif right.is_a? StringConstant
block.add( self , right , nil) #move the address, by "adding" to pc, ie pc relative
block.mov( Integer.new(self.used_register.next_reg_use) , right.length ) #and the length HACK TODO
block.mov( Integer.new(self.register.next_reg_use) , right.length ) #and the length HACK TODO
elsif right.is_a?(Boot::BootClass) or right.is_a?(Boot::MetaClass)
block.add( self , right , nil) #move the address, by "adding" to pc, ie pc relative
else