e8111c259b
fix last tests that required faked returns
2020-03-28 19:46:07 +02:00
a3effe29f6
adding integer compare tests and fixing returns
...
true, false and nll were not handled correctly as returns
returns assume int, and reduce. The solution (hack?) is to add fake numbers into true,false and nil that get returned from from the arm syscall
(and it works!, which means i can fix other tests now)
2020-03-28 18:41:59 +02:00
8dfcc0f5de
add decent method to get the programs return to interpreter
...
only had such methods in tests, but they really belong in code
also adding fake values to true ,false and nil
2020-03-28 18:39:49 +02:00
4bae5c418b
fix register use in putstring
...
was off by one, the syscall is write
and the first arg is file_descriptor
ie 1 == stdout
2020-03-26 11:24:56 +02:00
bc558d1f0d
do not copy name of method
...
so that the resolve can compare name identity
which is what is does, not equality
this (and some other bug) is crashing arm currently
2020-03-25 12:43:57 +02:00
90935bfbbc
risc is GREEN
...
totally, man.
Small fix in method missing fixed last block tests
(why, i do not know)
2020-03-22 15:58:19 +02:00
ddd1f4e296
fix interpreter syscall and rename return reg
...
returned int for puts was same name as implicit return int
2020-03-22 14:31:43 +02:00
be684c0c43
move message to stack_pointer
...
changing a bunch of register names
some of which get names now
2020-03-22 14:31:43 +02:00
a93a3c8af5
fix most interpreter tests
2020-03-22 14:31:43 +02:00
06ade75593
Fix non ssa issue
...
register instances were being shared across instructions
causing the setting to have side-effects
Fixed this by copying the register on write
(fixing the symptom rather than the cause, i'll make an issue)
2020-03-22 14:31:43 +02:00
d2e7c647d0
setting registers in the allocator
...
unfortunately the reg instances are spread across instructions
this causes problems when setting them
2020-03-22 14:31:43 +02:00
c890e8402b
change in register_names protocol
...
move to returning the attribute names
getting and setting can then be automated in the base class
2020-03-22 14:31:43 +02:00
0137056b89
change platform to return register names
...
not just the number of them
also adds protocol to map registers
(like message to r0 , or syscalls)
2020-03-22 14:31:43 +02:00
f13e6dcf57
fix releasing in allocator
...
fell into hash new trap, which reuses the object you give it. not good for mutable objects like the array.
also previous logic was broken in terms of machine vs ssa names
2020-03-22 14:31:43 +02:00
3f131a4018
start with register assigning
...
have to find a way to set them next
2020-03-22 14:31:43 +02:00
4f290ee246
basic liveliness for allocator
2020-03-22 14:31:43 +02:00
d0b734c57c
adding register_names to instruction protocol
2020-03-22 14:31:43 +02:00
8df1b8126f
add register names to allocator
...
make platform instantiate it
basic plumbing
2020-03-22 14:31:43 +02:00
500df01425
rename allocator to standard_allocator
...
planning to have platform dish it out
2020-03-22 14:31:43 +02:00
2e109a16dc
starting on risc allocation
...
inserting allocator stage in method translation
2020-03-22 14:31:43 +02:00
e4a79aac50
reset flags in interpreter
...
fix at least part of the problem why comparisons dont work
2020-03-22 14:31:43 +02:00
3ce6ed5263
fix putstring and puts
...
using syscall regs
2020-03-22 14:31:43 +02:00
17a7f29b0c
define and use syscall_XX registers
...
rather than use hardcoded r0 etc use syscall_X
change the syscalls and interpreter to use them
later use platform to map from syscall_X to actually used register (like r0 in arm)
2020-03-22 14:31:43 +02:00
7232c28ecd
operator also fell into ssa trap
...
relying on register identity
in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue
better now
2020-03-22 14:31:43 +02:00
5b0c1195e4
Fix interpreter and resolve method
...
Interpreter was not handling ssa correctly (ie overwriting)
Resolve was assuming wrong registers (also non ssa)
return value still broken
2020-03-22 14:31:43 +02:00
4db71c1c03
fix all uses of operators now they are ssa
2020-03-22 14:31:43 +02:00
0cde7c1d0a
debugging to find operator not being ssa
2020-03-22 14:31:43 +02:00
61fc8a3991
make operator_instruction single ass
...
create result register automatically
usually not used, but register allocation will sort that
2020-03-22 14:31:43 +02:00
1378745907
first interpreter tests
2020-03-22 14:31:43 +02:00
c16ed5ab3a
fix interpreter
...
by currently not checking for old register pattern
feels like wip, but passes (all but one)
2020-03-22 14:31:43 +02:00
f2250bc206
fix resolve and introduce method to chop strings to max
...
strings are 20 bytes. I want to implement the extension idea, just not now
2020-03-22 14:31:43 +02:00
2656bfacb2
create a reduce_int on RegisterSlot
...
that just passes through to RegisterValue by calling to_reg
2020-03-22 14:31:43 +02:00
8abcaa330b
fix allocate in builder
...
which accessed unknown types.
also moved assert_allocate to support
2020-03-22 14:31:43 +02:00
c9fedec230
add a way to bend the type for register_value
...
specifically for factories, where we know the type of next_object even it is not specified
2020-03-22 14:31:43 +02:00
6267bf3ad0
fix slot_to_reg to allow register indexes
...
we mostly use pre-calculated indexes, ie integers
but registers are allowed (in arm/risc), so we try to check the registers type at least is right.
The return is really a machine word, but we call it Object (yes, more work that way)
2020-03-22 14:31:43 +02:00
fb4fa598f2
fix get_internal_byte
...
improved operators and tests
some logic errors still
2020-03-22 14:31:43 +02:00
12fe0b9a10
add constants automatically
2020-03-22 14:31:43 +02:00
22d513d895
fix div4 and tests
...
also bug in reduce_int, compiler not carried through
2020-03-22 14:31:43 +02:00
eed9ba082f
Fix div10 and test
...
fix and use load_data (similar to load_constant)
and integrate into load_object when appropriate (ie for integers)
2020-03-22 14:31:43 +02:00
bd02f69824
reduce_int was overwriting register
...
No more. But the type question is open, ie what type does the resulting register have
2020-03-22 14:31:43 +02:00
53eb28fff4
load constant to create register names with class
...
Just the id_ did give no clue to the contents, just took care of the uniqueness.
Better for debugging
2020-03-22 14:31:43 +02:00
3ec5557ddb
fix builder logic error
...
and tests
2020-03-22 14:31:43 +02:00
9c5d17a3bb
Fix div10 without method_missing
...
but reanimate infer_type to auto create the needed regsiters
also some helpers
2020-03-22 14:31:43 +02:00
9a5e0f15cd
reannimate infer_type
...
now with a _purpose_
2020-03-22 14:31:43 +02:00
3688c967d3
Fix comparison macro
...
which leaves a definite need for instruction level testing
2020-03-22 14:31:43 +02:00
fd43fc9e5c
finally fixes the builder
2020-03-22 14:31:43 +02:00
db5a59f735
Unify instruction namings also dirs
...
Was getting confused myself, where it was instruction or instructions, when if the base class was inside or out of dir.
Now dirs are plural, and base class is inside.
2020-03-22 14:31:43 +02:00
f3d299208e
fix message_setup with new builder
2020-03-22 14:31:43 +02:00
ece1e8c87b
fix some more of builder
...
but still not all. removed some and fixed the register allocation in allocate_int
2020-03-22 14:31:43 +02:00
ff49ff50c0
Convert SimpleCall to new regs
...
Also fix bug in RegsiterValue/Slot with chain, where logic was dodgy and compiler not set
2020-03-22 14:31:43 +02:00
