Torsten Ruger
a50368c3aa
assembler will need redoing somewhat
...
with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
Torsten Ruger
82ab8ac4d3
add data objects
...
marker class (may change) to be able to check access
2018-03-25 18:22:02 +03:00
Torsten Ruger
bc4d4b428a
change boot to new hash syntax
2018-03-25 13:27:15 +03:00
Torsten Ruger
de7e02b0b8
remove IsSame branch from risc
...
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
Torsten Ruger
6a538624c5
remove NotSame from risc
...
instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
Torsten Ruger
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
Torsten Ruger
3ceb2c2f69
fix div10 return sequence
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did not return at all before
2018-03-24 16:51:26 +02:00
Torsten Ruger
267237b776
fix init method message setup
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was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
Torsten Ruger
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
Torsten Ruger
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
Torsten Ruger
a306c464b7
start using tmp registers at 1
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which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
Torsten Ruger
472b1a638a
add register logging and fix function return
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return semantics used to be different, now only register is given
2018-03-23 18:56:38 +02:00
Torsten Ruger
b4a18bc59b
mostly brackets and formatting
2018-03-23 18:55:23 +02:00
Torsten Ruger
34903829ca
fix interpreter test harness and start testing
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interpreter on debug for now
2018-03-22 18:54:40 +02:00
Torsten Ruger
9932d0bf33
add source to the to_s
2018-03-22 18:38:19 +02:00
Torsten Ruger
19afc376f4
fix local name being string (not symbol)
2018-03-22 21:08:13 +05:30
Torsten Ruger
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
Torsten Ruger
b5ef929c9c
add method to risc function call
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just so we still know at compile time
2018-03-21 19:05:53 +05:30
Torsten Ruger
fcbdba4804
simplify method entry exit codes
...
Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
Torsten Ruger
61a801b00c
Return to_risc
...
remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
Torsten Ruger
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
Torsten Ruger
fa797f722d
to_risc for NotSameCheck
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which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
Torsten Ruger
d98e55907e
first go at translating DynamicCall to risc
2018-03-21 11:51:10 +05:30
Torsten Ruger
77084dc894
fix unconditional jump
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and affected tests
2018-03-20 22:05:09 +05:30
Torsten Ruger
c8980595a3
start to test if
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truth check is only half done
2018-03-19 21:20:11 +05:30
Torsten Ruger
99ced4369a
adding Tue False and Nil Class to Parfait
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and boot
2018-03-19 21:18:56 +05:30
Torsten Ruger
c0a7f1d284
fix insertion and add assign send
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must implement send conversion before this makes sense
2018-03-19 13:19:42 +05:30
Torsten Ruger
66a160d8ab
fix code insertion in method
2018-03-19 13:05:08 +05:30
Torsten Ruger
0813312ddc
using compiler_for to create all building compilers
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unify api, create defaults and especially pass the right types into the
typed method creation
2018-03-18 22:08:35 +05:30
Torsten Ruger
c5ec532616
use common list for risc instruction
...
strange that that was not done before as the code was clearly copied
when extracting it
Fix bug for insertion
2018-03-18 10:36:01 +05:30
Torsten Ruger
9c052c78a7
fix most of slot_load to_risc
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higher orders not working yet
2018-03-17 21:32:09 +05:30
Torsten Ruger
cddc25a595
fixing tests for shifting constants into slots
2018-03-17 21:15:38 +05:30
Torsten Ruger
642f16b73a
adding cache entry to parfait
2018-03-17 19:03:39 +05:30
Torsten Ruger
16c8fcbf66
first local assignment risc test
...
comes with casualties
slot_load needs more work
2018-03-17 11:13:44 +05:30
Torsten Ruger
79bf416e58
collapsed slot classes into one
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different slot operation have different right sides
mom assignment tests work again
157 others don’t
2018-03-15 20:33:38 +05:30
Torsten Ruger
03a4e04f7e
rename self to receiver
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just because it is a keyword and can’t be used
2018-03-14 20:26:13 +05:30
Torsten Ruger
79b4b07ac4
style
2018-03-14 17:39:49 +05:30
Torsten Ruger
6fe13fc2b7
fix insertion to account for chains
2018-03-14 17:39:31 +05:30
Torsten Ruger
2aa7d37a83
rename locals to frame
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includes temps and tradition
2018-03-14 17:39:04 +05:30
Torsten Ruger
96800fd8fd
starting to_risc descent
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just fleshing it for now
2018-03-13 16:16:06 +05:30
Torsten Ruger
5fe0ba06ab
stash old vm
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moving on to getting mom to work and can’t have both
interpreter and elf broke, about 100 tests went
2018-03-11 17:02:42 +05:30
Torsten Ruger
f7aac1d1a4
polish docs
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and a bit of code style
2018-03-11 16:11:15 +05:30
Torsten Ruger
d6a2ea4cfc
fix dynamic resolve
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patch more like, real resolve method will have to be written
and put in there
2018-03-10 19:01:38 +05:30
Torsten Ruger
ba304f51df
using sof again, now rxf
2017-10-05 16:41:45 +03:00
Torsten Ruger
670ebd06cc
remove traces of salama
2017-08-29 18:38:51 +03:00
Torsten Ruger
aa79e41d1c
rename register to risc
...
seems to fit the layer much better as we really have a very reduced
instruction set
2017-01-19 09:02:29 +02:00
