must pass registers to slot_to_reg and reg_to_slot
as they are typed, those functions don't resolve on Risc, but the register type miscother changes from previous commits
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@ -45,8 +45,8 @@ module Risc
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sl = main_ticks(29)
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assert_equal Transfer , sl.class
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assert_equal :r0 , sl.from.symbol
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assert_equal :r1 , sl.to.symbol
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assert_equal 11 , @interpreter.get_register(:r1)
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assert_equal :r2 , sl.to.symbol
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assert_equal 11 , @interpreter.get_register(:r2)
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end
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def test_restore_message
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sl = main_ticks(30)
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@ -58,8 +58,8 @@ module Risc
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def test_save_sys_return
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sl = main_ticks(35)
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assert_equal RegToSlot , sl.class
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assert_equal :r1 , sl.register.symbol #return
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assert_equal :r2 , sl.array.symbol #parfait integer
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assert_equal :r2 , sl.register.symbol #return
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assert_equal :r3 , sl.array.symbol #parfait integer
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assert_equal 2 , sl.index
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end
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def test_return
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