From 3bc85805a44851fac4d7149d32281cfc036370cf Mon Sep 17 00:00:00 2001 From: Torsten Ruger Date: Sun, 15 Jul 2018 16:30:50 +0300 Subject: [PATCH] must pass registers to slot_to_reg and reg_to_slot as they are typed, those functions don't resolve on Risc, but the register type miscother changes from previous commits --- lib/mom/instruction/slot_load.rb | 3 +-- lib/risc/builder.rb | 8 +++++--- lib/risc/builtin/word.rb | 11 ++++++----- lib/risc/instructions/reg_to_slot.rb | 12 +++++------- lib/risc/instructions/slot_to_reg.rb | 9 ++++----- test/mom/send/test_send_simple_args.rb | 4 ++-- test/risc/interpreter/calling/test_puts.rb | 8 ++++---- 7 files changed, 27 insertions(+), 28 deletions(-) diff --git a/lib/mom/instruction/slot_load.rb b/lib/mom/instruction/slot_load.rb index ecb83136..c6ff2b5f 100644 --- a/lib/mom/instruction/slot_load.rb +++ b/lib/mom/instruction/slot_load.rb @@ -66,8 +66,7 @@ module Mom left = left.resolve_and_add( slot , const , compiler) slot = left_slots.shift end - left_index = left.resolve_index( slot ) - const << Risc.reg_to_slot(original_source, const.register , left, left_index) + const << Risc.reg_to_slot(original_source, const.register , left, slot) end end diff --git a/lib/risc/builder.rb b/lib/risc/builder.rb index 830de859..f8af1225 100644 --- a/lib/risc/builder.rb +++ b/lib/risc/builder.rb @@ -108,7 +108,7 @@ module Risc # Load the first argument, assumed to be integer def load_int_arg_at( source , at) int_arg = compiler.use_reg :Integer - add_slot_to_reg(source , :message , :arguments , int_arg ) + add_slot_to_reg(source , Risc.message_reg , :arguments , int_arg ) add_slot_to_reg(source , int_arg , at + 1, int_arg ) #1 for type return int_arg end @@ -135,8 +135,10 @@ module Risc def add_known(name) case name when :receiver - ret = compiler.use_reg compiler.resolve_type(:receiver) - add_slot_to_reg(" load self" , :message , :receiver , ret ) + message = Risc.message_reg + ret_type = message.resolve_new_type(:receiver, compiler) + ret = compiler.use_reg( ret_type ) + add_slot_to_reg(" load self" , message , :receiver , ret ) return ret when :space space = Parfait.object_space diff --git a/lib/risc/builtin/word.rb b/lib/risc/builtin/word.rb index f10871c4..273b4e63 100644 --- a/lib/risc/builtin/word.rb +++ b/lib/risc/builtin/word.rb @@ -7,10 +7,11 @@ module Risc def putstring( context) compiler = compiler_for(:Word , :putstring ,{}) builder = compiler.compiler_builder(compiler.source) - builder.add_slot_to_reg( "putstring" , :message , :receiver , :new_message ) + new_message = Risc.message_reg.get_new_left(:receiver , compiler) + builder.add_slot_to_reg( "putstring" , Risc.message_reg , :receiver , new_message ) index = Parfait::Word.get_length_index - reg = RegisterValue.new(:r2 , :Integer) - builder.add_slot_to_reg( "putstring" , :new_message , index , reg ) + index_reg = RegisterValue.new(:r2 , :Integer) + builder.add_slot_to_reg( "putstring" , new_message , index , index_reg ) Risc::Builtin::Object.emit_syscall( builder , :putstring ) compiler.add_mom( Mom::ReturnSequence.new) compiler @@ -28,7 +29,7 @@ module Risc builder.add_byte_to_reg( source , me , index , me) builder.add_new_int(source, me , index) # and put it back into the return value - builder.add_reg_to_slot( source , index , :message , :return_value) + builder.add_reg_to_slot( source , index , Risc.message_reg , :return_value) compiler.add_mom( Mom::ReturnSequence.new) return compiler end @@ -46,7 +47,7 @@ module Risc builder.reduce_int( source + " fix arg", index ) builder.add_reg_to_byte( source , value , me , index) value = builder.load_int_arg_at(source , 1 ) - builder.add_reg_to_slot( source , value , :message , :return_value) + builder.add_reg_to_slot( source , value , Risc.message_reg , :return_value) compiler.add_mom( Mom::ReturnSequence.new) return compiler end diff --git a/lib/risc/instructions/reg_to_slot.rb b/lib/risc/instructions/reg_to_slot.rb index ffe603bb..e1953748 100644 --- a/lib/risc/instructions/reg_to_slot.rb +++ b/lib/risc/instructions/reg_to_slot.rb @@ -14,13 +14,11 @@ module Risc end # Produce a RegToSlot instruction. - # From and to are registers or symbols that can be transformed to a register by resolve_to_register - # (which are precisely the symbols :message or :new_message. or a register) - # index resolves with resolve_to_index. - def self.reg_to_slot( source , from_reg , to , index ) - from = resolve_to_register from_reg - index = resolve_to_index( to , index) - to = resolve_to_register to + # From and to are registers + # index may be a Symbol in which case is resolves with resolve_index. + def self.reg_to_slot( source , from , to , index ) + raise "Not register #{to}" unless RegisterValue.look_like_reg(to) + index = to.resolve_index(index) if index.is_a?(Symbol) RegToSlot.new( source, from , to , index) end diff --git a/lib/risc/instructions/slot_to_reg.rb b/lib/risc/instructions/slot_to_reg.rb index feef4f08..0ea8185b 100644 --- a/lib/risc/instructions/slot_to_reg.rb +++ b/lib/risc/instructions/slot_to_reg.rb @@ -14,12 +14,11 @@ module Risc end # Produce a SlotToReg instruction. - # Array and to are registers or symbols that can be transformed to a register by resolve_to_register - # index resolves with resolve_to_index. + # Array and to are registers + # index may be a Symbol in which case is resolves with resolve_index. def self.slot_to_reg( source , array , index , to) - index = resolve_to_index( array , index) - array = resolve_to_register( array ) - to = resolve_to_register( to ) + raise "Not register #{array}" unless RegisterValue.look_like_reg(array) + index = array.resolve_index(index) if index.is_a?(Symbol) SlotToReg.new( source , array , index , to) end end diff --git a/test/mom/send/test_send_simple_args.rb b/test/mom/send/test_send_simple_args.rb index 81c30ee3..ca6eb398 100644 --- a/test/mom/send/test_send_simple_args.rb +++ b/test/mom/send/test_send_simple_args.rb @@ -41,7 +41,7 @@ module Risc def test_load_args produced = produce_body assert_equal SlotToReg , produced.next(base+2).class - assert_equal :r3 , produced.next(base+2).register.symbol + assert_equal :r2 , produced.next(base+2).register.symbol assert_equal :r2 , produced.next(base+2).array.symbol assert_equal 8 , produced.next(base+2).index end @@ -49,7 +49,7 @@ module Risc produced = produce_body assert_equal RegToSlot , produced.next(base+3).class assert_equal :r1 , produced.next(base+3).register.symbol - assert_equal :r3 , produced.next(base+3).array.symbol + assert_equal :r2 , produced.next(base+3).array.symbol assert_equal 1 , produced.next(base+3).index , "first arg must have index 1" end def test_load_label diff --git a/test/risc/interpreter/calling/test_puts.rb b/test/risc/interpreter/calling/test_puts.rb index 2c6e9e69..f8ad5030 100644 --- a/test/risc/interpreter/calling/test_puts.rb +++ b/test/risc/interpreter/calling/test_puts.rb @@ -45,8 +45,8 @@ module Risc sl = main_ticks(29) assert_equal Transfer , sl.class assert_equal :r0 , sl.from.symbol - assert_equal :r1 , sl.to.symbol - assert_equal 11 , @interpreter.get_register(:r1) + assert_equal :r2 , sl.to.symbol + assert_equal 11 , @interpreter.get_register(:r2) end def test_restore_message sl = main_ticks(30) @@ -58,8 +58,8 @@ module Risc def test_save_sys_return sl = main_ticks(35) assert_equal RegToSlot , sl.class - assert_equal :r1 , sl.register.symbol #return - assert_equal :r2 , sl.array.symbol #parfait integer + assert_equal :r2 , sl.register.symbol #return + assert_equal :r3 , sl.array.symbol #parfait integer assert_equal 2 , sl.index end def test_return