must pass registers to slot_to_reg and reg_to_slot
as they are typed, those functions don't resolve on Risc, but the register type miscother changes from previous commits
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@ -66,8 +66,7 @@ module Mom
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left = left.resolve_and_add( slot , const , compiler)
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slot = left_slots.shift
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end
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left_index = left.resolve_index( slot )
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const << Risc.reg_to_slot(original_source, const.register , left, left_index)
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const << Risc.reg_to_slot(original_source, const.register , left, slot)
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end
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end
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@ -108,7 +108,7 @@ module Risc
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# Load the first argument, assumed to be integer
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def load_int_arg_at( source , at)
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int_arg = compiler.use_reg :Integer
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add_slot_to_reg(source , :message , :arguments , int_arg )
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add_slot_to_reg(source , Risc.message_reg , :arguments , int_arg )
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add_slot_to_reg(source , int_arg , at + 1, int_arg ) #1 for type
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return int_arg
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end
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@ -135,8 +135,10 @@ module Risc
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def add_known(name)
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case name
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when :receiver
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ret = compiler.use_reg compiler.resolve_type(:receiver)
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add_slot_to_reg(" load self" , :message , :receiver , ret )
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message = Risc.message_reg
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ret_type = message.resolve_new_type(:receiver, compiler)
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ret = compiler.use_reg( ret_type )
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add_slot_to_reg(" load self" , message , :receiver , ret )
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return ret
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when :space
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space = Parfait.object_space
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@ -7,10 +7,11 @@ module Risc
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def putstring( context)
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compiler = compiler_for(:Word , :putstring ,{})
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builder = compiler.compiler_builder(compiler.source)
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builder.add_slot_to_reg( "putstring" , :message , :receiver , :new_message )
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new_message = Risc.message_reg.get_new_left(:receiver , compiler)
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builder.add_slot_to_reg( "putstring" , Risc.message_reg , :receiver , new_message )
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index = Parfait::Word.get_length_index
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reg = RegisterValue.new(:r2 , :Integer)
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builder.add_slot_to_reg( "putstring" , :new_message , index , reg )
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index_reg = RegisterValue.new(:r2 , :Integer)
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builder.add_slot_to_reg( "putstring" , new_message , index , index_reg )
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Risc::Builtin::Object.emit_syscall( builder , :putstring )
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compiler.add_mom( Mom::ReturnSequence.new)
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compiler
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@ -28,7 +29,7 @@ module Risc
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builder.add_byte_to_reg( source , me , index , me)
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builder.add_new_int(source, me , index)
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# and put it back into the return value
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builder.add_reg_to_slot( source , index , :message , :return_value)
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builder.add_reg_to_slot( source , index , Risc.message_reg , :return_value)
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compiler.add_mom( Mom::ReturnSequence.new)
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return compiler
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end
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@ -46,7 +47,7 @@ module Risc
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builder.reduce_int( source + " fix arg", index )
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builder.add_reg_to_byte( source , value , me , index)
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value = builder.load_int_arg_at(source , 1 )
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builder.add_reg_to_slot( source , value , :message , :return_value)
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builder.add_reg_to_slot( source , value , Risc.message_reg , :return_value)
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compiler.add_mom( Mom::ReturnSequence.new)
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return compiler
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end
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@ -14,13 +14,11 @@ module Risc
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end
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# Produce a RegToSlot instruction.
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# From and to are registers or symbols that can be transformed to a register by resolve_to_register
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# (which are precisely the symbols :message or :new_message. or a register)
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# index resolves with resolve_to_index.
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def self.reg_to_slot( source , from_reg , to , index )
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from = resolve_to_register from_reg
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index = resolve_to_index( to , index)
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to = resolve_to_register to
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# From and to are registers
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# index may be a Symbol in which case is resolves with resolve_index.
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def self.reg_to_slot( source , from , to , index )
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raise "Not register #{to}" unless RegisterValue.look_like_reg(to)
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index = to.resolve_index(index) if index.is_a?(Symbol)
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RegToSlot.new( source, from , to , index)
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end
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@ -14,12 +14,11 @@ module Risc
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end
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# Produce a SlotToReg instruction.
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# Array and to are registers or symbols that can be transformed to a register by resolve_to_register
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# index resolves with resolve_to_index.
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# Array and to are registers
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# index may be a Symbol in which case is resolves with resolve_index.
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def self.slot_to_reg( source , array , index , to)
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index = resolve_to_index( array , index)
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array = resolve_to_register( array )
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to = resolve_to_register( to )
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raise "Not register #{array}" unless RegisterValue.look_like_reg(array)
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index = array.resolve_index(index) if index.is_a?(Symbol)
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SlotToReg.new( source , array , index , to)
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end
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end
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@ -41,7 +41,7 @@ module Risc
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def test_load_args
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produced = produce_body
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assert_equal SlotToReg , produced.next(base+2).class
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assert_equal :r3 , produced.next(base+2).register.symbol
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assert_equal :r2 , produced.next(base+2).register.symbol
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assert_equal :r2 , produced.next(base+2).array.symbol
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assert_equal 8 , produced.next(base+2).index
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end
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@ -49,7 +49,7 @@ module Risc
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produced = produce_body
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assert_equal RegToSlot , produced.next(base+3).class
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assert_equal :r1 , produced.next(base+3).register.symbol
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assert_equal :r3 , produced.next(base+3).array.symbol
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assert_equal :r2 , produced.next(base+3).array.symbol
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assert_equal 1 , produced.next(base+3).index , "first arg must have index 1"
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end
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def test_load_label
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@ -45,8 +45,8 @@ module Risc
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sl = main_ticks(29)
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assert_equal Transfer , sl.class
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assert_equal :r0 , sl.from.symbol
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assert_equal :r1 , sl.to.symbol
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assert_equal 11 , @interpreter.get_register(:r1)
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assert_equal :r2 , sl.to.symbol
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assert_equal 11 , @interpreter.get_register(:r2)
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end
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def test_restore_message
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sl = main_ticks(30)
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@ -58,8 +58,8 @@ module Risc
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def test_save_sys_return
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sl = main_ticks(35)
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assert_equal RegToSlot , sl.class
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assert_equal :r1 , sl.register.symbol #return
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assert_equal :r2 , sl.array.symbol #parfait integer
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assert_equal :r2 , sl.register.symbol #return
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assert_equal :r3 , sl.array.symbol #parfait integer
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assert_equal 2 , sl.index
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end
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def test_return
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