must pass registers to slot_to_reg and reg_to_slot
as they are typed, those functions don't resolve on Risc, but the register type miscother changes from previous commits
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@ -41,7 +41,7 @@ module Risc
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def test_load_args
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produced = produce_body
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assert_equal SlotToReg , produced.next(base+2).class
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assert_equal :r3 , produced.next(base+2).register.symbol
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assert_equal :r2 , produced.next(base+2).register.symbol
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assert_equal :r2 , produced.next(base+2).array.symbol
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assert_equal 8 , produced.next(base+2).index
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end
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@ -49,7 +49,7 @@ module Risc
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produced = produce_body
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assert_equal RegToSlot , produced.next(base+3).class
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assert_equal :r1 , produced.next(base+3).register.symbol
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assert_equal :r3 , produced.next(base+3).array.symbol
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assert_equal :r2 , produced.next(base+3).array.symbol
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assert_equal 1 , produced.next(base+3).index , "first arg must have index 1"
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end
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def test_load_label
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