must pass registers to slot_to_reg and reg_to_slot

as they are typed, those functions don't resolve on Risc, but the register type
miscother changes from previous commits
This commit is contained in:
Torsten Ruger
2018-07-15 16:30:50 +03:00
parent f31d22d901
commit 3bc85805a4
7 changed files with 27 additions and 28 deletions

View File

@ -41,7 +41,7 @@ module Risc
def test_load_args
produced = produce_body
assert_equal SlotToReg , produced.next(base+2).class
assert_equal :r3 , produced.next(base+2).register.symbol
assert_equal :r2 , produced.next(base+2).register.symbol
assert_equal :r2 , produced.next(base+2).array.symbol
assert_equal 8 , produced.next(base+2).index
end
@ -49,7 +49,7 @@ module Risc
produced = produce_body
assert_equal RegToSlot , produced.next(base+3).class
assert_equal :r1 , produced.next(base+3).register.symbol
assert_equal :r3 , produced.next(base+3).array.symbol
assert_equal :r2 , produced.next(base+3).array.symbol
assert_equal 1 , produced.next(base+3).index , "first arg must have index 1"
end
def test_load_label