2014-05-10 14:34:05 +02:00
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require_relative "logic_helper"
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2014-05-03 14:13:15 +02:00
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2014-05-03 21:18:04 +02:00
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module Arm
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2014-05-03 14:13:15 +02:00
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2014-05-05 21:21:11 +02:00
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class LogicInstruction < Vm::LogicInstruction
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include Arm::Constants
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2014-05-16 09:42:25 +02:00
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def initialize(first , attributes)
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super(first , attributes)
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2014-05-16 18:56:13 +02:00
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@attributes[:update_status] = 0 if @attributes[:update_status] == nil
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2014-05-14 09:47:30 +02:00
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@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
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2014-05-05 21:21:11 +02:00
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@operand = 0
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2014-05-16 10:27:30 +02:00
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@left = @attributes[:left]
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raise "Left arg must be given #{inspect}" unless @left
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2014-05-16 11:55:51 +02:00
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@immediate = 0
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2014-05-05 21:21:11 +02:00
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end
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2014-05-16 09:42:25 +02:00
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# arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
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def length
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4
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end
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2014-05-16 09:54:56 +02:00
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# Build representation for source value
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2014-05-16 10:27:30 +02:00
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def build
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2014-05-16 11:55:51 +02:00
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right = @attributes[:right]
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2014-05-16 10:27:30 +02:00
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if @left.is_a?(Vm::StringConstant)
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2014-05-16 09:42:25 +02:00
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# do pc relative addressing with the difference to the instuction
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2014-05-16 11:55:51 +02:00
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# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
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right = @left.position - self.position - 8
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2014-05-16 09:54:56 +02:00
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@left = :pc
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2014-05-16 09:42:25 +02:00
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end
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2014-05-16 11:55:51 +02:00
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# automatic wrapping, for machine internal code and testing
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if( right.is_a? Fixnum )
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right = Vm::IntegerConstant.new( right )
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2014-05-16 09:42:25 +02:00
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end
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2014-05-16 11:55:51 +02:00
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if (right.is_a?(Vm::IntegerConstant))
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if (right.integer.fits_u8?)
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2014-05-16 09:42:25 +02:00
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# no shifting needed
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2014-05-16 11:55:51 +02:00
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@operand = right.integer
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@immediate = 1
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elsif (op_with_rot = calculate_u8_with_rr(right))
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2014-05-16 09:42:25 +02:00
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@operand = op_with_rot
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2014-05-16 11:55:51 +02:00
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@immediate = 1
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2014-05-16 09:42:25 +02:00
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raise "hmm"
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else
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2014-05-16 11:55:51 +02:00
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raise "cannot fit numeric literal argument in operand #{right.inspect}"
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2014-05-16 09:42:25 +02:00
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end
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2014-05-16 11:55:51 +02:00
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elsif (right.is_a?(Symbol) or right.is_a?(Vm::Integer))
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@operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
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@immediate = 0 # ie not immediate is register
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else
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raise "invalid operand argument #{right.inspect} , #{inspect}"
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end
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2014-05-16 16:31:01 +02:00
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shift_handling
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2014-05-16 09:42:25 +02:00
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end
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def assemble(io)
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build
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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2014-05-16 11:55:51 +02:00
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val = shift(@operand , 0)
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2014-05-16 09:42:25 +02:00
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val |= shift(reg_code(@first) , 12)
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2014-05-16 09:54:56 +02:00
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val |= shift(reg_code(@left) , 12+4)
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2014-05-16 18:56:13 +02:00
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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2014-05-16 09:42:25 +02:00
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val |= shift(op_bit_code , 12+4+4 +1)
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2014-05-16 11:55:51 +02:00
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val |= shift(@immediate , 12+4+4 +1+4)
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2014-05-16 09:42:25 +02:00
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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io.write_uint32 val
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end
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def shift val , by
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2014-05-16 10:27:30 +02:00
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raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
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2014-05-16 09:42:25 +02:00
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val << by
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end
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2014-05-03 14:13:15 +02:00
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end
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end
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