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Fix is_riscv_isa

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This commit is contained in:
Quentin Legot 2023-03-31 15:34:04 +02:00
parent b4b7eb69c2
commit 453de4b704
1 changed files with 4 additions and 1 deletions
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5
src/simulator/loader.rs
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@ -91,7 +91,7 @@ impl Loader {
/// return true if specified target instruction set architecture is RISCV /// return true if specified target instruction set architecture is RISCV
fn is_riscv_isa(&self) -> bool { fn is_riscv_isa(&self) -> bool {
self.bytes.get(0x12) == Option::Some(&0xf7) self.get_u16_value(0x12) == Option::Some(0xf3)
} }
/// memory address of the entry point from where the process starts its execution /// memory address of the entry point from where the process starts its execution
@ -198,6 +198,9 @@ mod test {
assert_eq!(true, loader.is_elf()); assert_eq!(true, loader.is_elf());
assert_eq!(false, loader.is_32bits()); assert_eq!(false, loader.is_32bits());
assert_eq!(false, loader.check_endianess()); assert_eq!(false, loader.check_endianess());
assert_eq!(true, loader.is_system_v_elf());
assert_eq!(true, loader.is_riscv_isa());
assert_eq!(Option::Some(1), loader.get_version());
} }
} }