diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs
index 2f8a292..904bc87 100644
--- a/src/simulator/loader.rs
+++ b/src/simulator/loader.rs
@@ -91,7 +91,7 @@ impl Loader {
 
     /// return true if specified target instruction set architecture is RISCV
     fn is_riscv_isa(&self) -> bool {
-        self.bytes.get(0x12) == Option::Some(&0xf7)
+        self.get_u16_value(0x12) == Option::Some(0xf3)
     }
 
     /// memory address of the entry point from where the process starts its execution
@@ -198,6 +198,9 @@ mod test {
         assert_eq!(true, loader.is_elf());
         assert_eq!(false, loader.is_32bits());
         assert_eq!(false, loader.check_endianess());
+        assert_eq!(true, loader.is_system_v_elf());
+        assert_eq!(true, loader.is_riscv_isa());
+        assert_eq!(Option::Some(1), loader.get_version());
     }
 
 }
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