From 453de4b704ea2dda6cc02cfa5f991e70e9945130 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Fri, 31 Mar 2023 15:34:04 +0200 Subject: [PATCH] Fix is_riscv_isa --- src/simulator/loader.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs index 2f8a292..904bc87 100644 --- a/src/simulator/loader.rs +++ b/src/simulator/loader.rs @@ -91,7 +91,7 @@ impl Loader { /// return true if specified target instruction set architecture is RISCV fn is_riscv_isa(&self) -> bool { - self.bytes.get(0x12) == Option::Some(&0xf7) + self.get_u16_value(0x12) == Option::Some(0xf3) } /// memory address of the entry point from where the process starts its execution @@ -198,6 +198,9 @@ mod test { assert_eq!(true, loader.is_elf()); assert_eq!(false, loader.is_32bits()); assert_eq!(false, loader.check_endianess()); + assert_eq!(true, loader.is_system_v_elf()); + assert_eq!(true, loader.is_riscv_isa()); + assert_eq!(Option::Some(1), loader.get_version()); } } \ No newline at end of file