BurritOS/src/simulator/machine.rs

use std::ops::{Add, Sub};

use super::{decode::{Instruction, decode}};
use super::global::*;
/// doit disparaitre
const MEM_SIZE : usize = 4096;

trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}

impl RegisterNum for i64 {}

impl RegisterNum for f32 {}

struct Register<U: RegisterNum> {
	register: [U; 32]
}

impl<U: RegisterNum> Register<U> {

	pub fn get_reg(&self, position: usize) -> U {
		self.register[position]
	}

}

impl Register<i64> {

	pub fn init() -> Register<i64> {
		Register { 
			register: [0i64; 32]
		}
	}

	pub fn set_reg(&mut self, position: usize, value: i64) {
		if position != 0 {
			self.register[position] = value;
		} else {
			// Panic ou rien ? (dans le doute pour le moment panic)
			unreachable!("You can't write to zero register")
		}
	}

}

impl Register<f32> {

	pub fn init() -> Register<f32> {
		Register { 
			register: [0f32; 32]
		}
	}

	pub fn set_reg(&mut self, position: usize, value: f32) {
		self.register[position] = value;
	}

}

pub struct Machine {
	pub pc : u64,
	pub int_reg : Register<i64>,
	pub instructions : [u64 ; 100],
	pub main_memory : [u8 ; MEM_SIZE],
	pub shiftmask : [u64 ; 64]
	// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
	//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
}


impl Machine {

	pub fn _init_machine() -> Machine {	
		let mut shiftmask : [u64 ; 64] = [0 ; 64];
		let mut value : u64 = 0xffffffff;

		value = (value << 32) + value;
		for item in &mut shiftmask {
			*item = value;
			value >>= 1;
		}

		// let int_reg = Register::<i64>::init();
		// let fp_reg = Register::<f32>::init();

		Machine {
			pc : 0,
			instructions : [0 ; 100],
			int_reg : Register::<i64>::init(),
			main_memory : [0 ; MEM_SIZE],
			shiftmask
		}
		
	}

	/// Read from main memory of the machine
	///
	/// `panic!` when size is not 1, 2, 4 or 8
	/// 
	/// ### Parameters
	///
	/// - **machine** which contains the main memory
	/// - **size** the number of bytes to read (1, 2, 4, 8)
	/// - **address** in the memory to read
	pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
		if ![1, 2, 4, 8].contains(&size) {
			panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
		}

		let mut ret: u64 = 0;
		for i in 0..size {
			ret <<= 8;
			ret += machine.main_memory[address + i as usize] as u64;
		}
		ret
	}

	/// Write to the main memory of the machine
	/// 
	/// `panic!` when size is not 1, 2, 4 or 8
	/// 
	/// ### Parameters
	/// 
	/// - **machine** contains the memory
	/// - **size** the number of bytes to write (1, 2, 4 or 8)
	/// - **address** the address to write to
	/// - **value** data to be written
	pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: u64) {
		if ![1, 2, 4, 8].contains(&size) {
			panic!("ERROR write_memory: WRONG `size` PARAMETER ({}), must be 1, 2, 4 or 8", size)
		}
		for i in 0..size as usize {
			let inv_i = size as usize - i - 1;
			machine.main_memory[address + i as usize] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8;
		}
	}

	/// Execute the instructions table of a machine putted in param
	/// 
	/// ### Parameters
	/// 
	/// - **machine** which contains a table of instructions
	pub fn run(machine : Machine){
		let mut m = machine;
		loop{
			Machine::one_instruction(&mut m);
		}
	}

	/// execute the current instruction
	/// 
	/// ### Parameters
	/// 
	/// - **machine** which contains a table of instructions and a pc to the actual instruction
	pub fn one_instruction(machine :&mut Machine) {
	
		let unsigned_reg1 : u64;
		let unsigned_reg2 : u64;
		let long_result : i128;
		 
		 /*__int128 longResult;
  		int32_t local_data_a, local_data_b;
  		int64_t localLongResult;
  		uint32_t local_data_aUnsigned, local_data_bUnsigned;
  		int32_t localResult;
  		float localFloat;
  		uint64_t value;*/
	
		if machine.instructions.len() <= machine.pc as usize {
			println!("ERROR : number max of instructions rushed");
			return ;
		}

		let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
		
		
		match inst.opcode {
			RISCV_LUI => {
				machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
			},
			RISCV_AUIPC => {
				machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
			},
			RISCV_JAL => {
				machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
				machine.pc += inst.imm21_1_signed as u64 - 4;
			},
			RISCV_JALR => {
				let tmp = machine.pc;
				machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
				machine.int_reg.set_reg(inst.rd as usize, tmp as i64);
			},

			//******************************************************************************************
  			// Treatment for: BRANCH INSTRUCTIONS
			RISCV_BR => {
				match inst.funct3 {
					RISCV_BR_BEQ => {
						if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
							machine.pc += inst.imm13_signed as u64 - 4;
						}
					},
					RISCV_BR_BNE => {
						if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
							machine.pc += inst.imm13_signed as u64 - 4;
						}
					},
					RISCV_BR_BLT => {
						if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
							machine.pc += inst.imm13_signed as u64 - 4;
						}
					},
					RISCV_BR_BGE => {
						if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
							machine.pc += inst.imm13_signed as u64 - 4;
						}
					},
					RISCV_BR_BLTU => {
						if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
							machine.pc += inst.imm13_signed as u64 - 4;
						}
					},
					RISCV_BR_BGEU => {
						if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
							machine.pc += inst.imm13_signed as u64 - 4;
						}
					},
					_ => {
						panic!("In BR switch case, this should never happen... Instr was {}", inst.value);
					}
				}
			},

			//******************************************************************************************
    		// Treatment for: LOAD INSTRUCTIONS
			RISCV_LD => {
				match inst.funct3 {
					RISCV_LD_LB | RISCV_LD_LBU => {
						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
					},
					RISCV_LD_LH | RISCV_LD_LHU => {
						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
					},
					RISCV_LD_LW | RISCV_LD_LWU => {
						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
					},
					RISCV_LD_LD => {
						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
					},
					_ => {
						panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
					}
				}
			},
			// store instructions
			RISCV_ST => {
				match inst.funct3 {
					RISCV_ST_STB => {
						Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
					},
					RISCV_ST_STH => {
						Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
					},
					RISCV_ST_STW => {
						Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
					},
					RISCV_ST_STD => {
						Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
					},
					_ => {
						panic!("In ST switch case, this should never happen... Instr was {}", inst.value);
					}
				}
			}
			//******************************************************************************************
    		// Treatment for: OPI INSTRUCTIONS
			RISCV_OPI => {
				match inst.funct3 {
					RISCV_OPI_ADDI => {
						machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64);
					},
					RISCV_OPI_SLTI => {
						machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } );
					},
					RISCV_OPI_XORI => {
						machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64);
					},
					RISCV_OPI_ORI => {
						machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64);
					},
					RISCV_OPI_ANDI => {
						machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64);
					},
					RISCV_OPI_SLLI => {
						machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt);
					},
					RISCV_OPI_SRI => {
						if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
							machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64;
						} else { // SRAI
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;	
						}
					}
					_ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); }
				}
			},
			
			RISCV_OP => {
				if inst.funct7 == 1 {
					match inst.funct3 {
						RISCV_OP_M_MUL => {
							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
							machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64;
						},
						RISCV_OP_M_MULH => {
							long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
							machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64;
						},
						RISCV_OP_M_MULHSU => {
							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
            				long_result   = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
            				machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as i64;
						},
						// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
						/*
						* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
						* WHAT DA HECK
						*/
						RISCV_OP_M_MULHU => {
							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
            						unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
            						long_result   = (unsigned_reg1 * unsigned_reg2) as i128;
	   						machine.int_reg[inst.rd as usize]    = ((long_result >> 64) & 0xffffffffffffffff) as i64;
						},
						RISCV_OP_M_DIV => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize];
						}
						_ => {
							panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
						}
					}
				} else {
					match inst.funct3 {
						RISCV_OP_ADD => {
							if inst.funct7 == RISCV_OP_ADD_ADD {
								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
							} else {
								machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
							}
						},
						RISCV_OP_SLL => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
						},
						RISCV_OP_SLT => {
							if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
								machine.int_reg[inst.rd as usize] = 1;
							} else {
								machine.int_reg[inst.rd as usize] = 0;
							}
						},
						RISCV_OP_SLTU => {
							unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
							unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
							if unsigned_reg1 < unsigned_reg2 {
								machine.int_reg[inst.rd as usize] = 1;
							} else {
								machine.int_reg[inst.rd as usize] = 0;
							}
						},
						RISCV_OP_XOR => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
						},
						RISCV_OP_SR => {
						// RISCV_OP_SR_SRL inaccessible
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
						},
						RISCV_OP_OR => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
						},
						RISCV_OP_AND => {
							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
						},
						_ => {
							panic!("RISCV_OP undefined case\n");
						}
					}//LA
				}
			},
			//******************************************************************************************
    		// Treatment for: OPW INSTRUCTIONS
			RISCV_OPW => {
				if inst.funct7 == 1 {
					let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
					let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
					let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
					let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;

					// Match case for multiplication operations (in standard extension RV32M)
					match inst.funct3 {
						RISCV_OPW_M_MULW => {
							machine.int_reg[inst.rd as usize] = local_data_a * local_data_b;
						},
						RISCV_OPW_M_DIVW => {
							machine.int_reg[inst.rd as usize] = local_data_a / local_data_b;
						},
						RISCV_OPW_M_DIVUW => {
							machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned;
						},
						RISCV_OPW_M_REMW => {
							machine.int_reg[inst.rd as usize] = local_data_a % local_data_b;
						},
						RISCV_OPW_M_REMUW => {
							machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned;
						},
						_ => {
							panic!("this instruction ({}) doesn't exists", inst.value);
						}
					}
				} else {
					let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
					let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;

					// Match case for base OP operation
					match inst.funct3 {
						RISCV_OPW_ADDSUBW => {
							if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
								machine.int_reg[inst.rd as usize] = local_dataa + local_datab;
							} else { // SUBW
								machine.int_reg[inst.rd as usize] = local_dataa - local_datab;
							}
						},
						RISCV_OPW_SLLW => {
							machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f);
						},
						RISCV_OPW_SRW => {
							if inst.funct7 == RISCV_OPW_SRW_SRLW {
								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64;
							} else { // SRAW
								machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f);
							}
						},
						_ => {
							panic!("this instruction ({}) doesn't exists", inst.value);
						}
					}
				}
			}
			_ => { panic!("{} opcode non géré", inst.opcode)},
		}

		machine.pc += 4;

	}
}

#[cfg(test)]
 mod test {
    use crate::simulator::machine::Machine;

	#[test]
	fn test_read_memory() {
		let mut m = Machine::_init_machine();
    	m.main_memory[4] = 43;
    	m.main_memory[5] = 150;
		assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4));
	}

	#[test]
	fn test_write_memory() {
		let mut m = Machine::_init_machine();
		Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
		assert_eq!(43, m.main_memory[6]);
		assert_eq!(150, m.main_memory[7]);
	}
}