OPW instructions
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Baptiste
parent
98f4c0b67e
commit
d021fc3565
@ -9,7 +9,8 @@ pub struct Machine {
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pub pc : u32,
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pub int_reg : [u32 ; 32],
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pub instructions : [u32 ; 100],
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pub main_memory : [u8 ; MEM_SIZE]
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pub main_memory : [u8 ; MEM_SIZE],
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pub shiftmask : [u32 ; 32]
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// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
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//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
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}
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@ -18,12 +19,21 @@ pub struct Machine {
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impl Machine {
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pub fn _init_machine() -> Machine {
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let mut shiftmask : [u32 ; 32] = [0 ; 32];
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let mut value : u32 = 0xffff;
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value = (value << 16) + value;
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for i in 0..32 {
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shiftmask[i] = value;
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value = value >> 1;
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}
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Machine {
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pc : 0,
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instructions : [0 ; 100],
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int_reg : [0 ; 32],
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main_memory : [0 ; MEM_SIZE]
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main_memory : [0 ; MEM_SIZE],
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shiftmask : shiftmask
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}
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}
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@ -68,6 +78,13 @@ impl Machine {
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},
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RISCV_OPI_SLLI => {
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machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
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},
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RISCV_OPI_SRI => {
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if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
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machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize];
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} else { // SRAI
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machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt);
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}
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}
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_ => { println!("{} inconnu", inst.funct3); }
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}
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@ -123,6 +140,65 @@ impl Machine {
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println!("RISCV_OP undefined case\n");
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}
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}
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},
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//******************************************************************************************
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// Treatment for: OPW INSTRUCTIONS
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RISCV_OPW => {
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if inst.funct7 == 1 {
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let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
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let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
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let localDataaUnsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
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let localDatabUnsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
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// Match case for multiplication operations (in standard extension RV32M)
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match inst.funct3 {
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RISCV_OPW_M_MULW => {
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machine.int_reg[inst.rd as usize] = localDataa * localDatab;
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},
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RISCV_OPW_M_DIVW => {
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machine.int_reg[inst.rd as usize] = localDataa / localDatab;
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},
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RISCV_OPW_M_DIVUW => {
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machine.int_reg[inst.rd as usize] = localDataaUnsigned / localDatabUnsigned;
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},
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RISCV_OPW_M_REMW => {
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machine.int_reg[inst.rd as usize] = localDataa % localDatab;
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},
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RISCV_OPW_M_REMUW => {
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machine.int_reg[inst.rd as usize] = localDataaUnsigned % localDatabUnsigned;
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},
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_ => {
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println!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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} else {
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let localDataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
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let localDatab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
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// Match case for base OP operation
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match inst.funct3 {
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RISCV_OPW_ADDSUBW => {
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if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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machine.int_reg[inst.rd as usize] = localDataa + localDatab;
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} else { // SUBW
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machine.int_reg[inst.rd as usize] = localDataa - localDatab;
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}
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},
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RISCV_OPW_SLLW => {
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machine.int_reg[inst.rd as usize] = localDataa << (localDatab & 0x1f);
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},
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RISCV_OPW_SRW => {
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if inst.funct7 == RISCV_OPW_SRW_SRLW {
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machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f) & machine.shiftmask[32 + localDatab as usize];
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} else { // SRAW
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machine.int_reg[inst.rd as usize] = localDataa >> (localDatab & 0x1f);
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}
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},
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_ => {
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println!("this instruction ({}) doesn't exists", inst.value);
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}
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}
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}
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}
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_ => { println!("{} opcode non géré", inst.opcode)},
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}
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32
src/print.rs
32
src/print.rs
@ -130,6 +130,38 @@ pub const RISCV_FP_FCMP_FLE: u8 = 0;
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pub const RISCV_FP_FMVW: u8 = 0x78;
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pub const RISCV_OP_M: u8 = 0x1;
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pub const RISCV_OP_M_MUL: u8 = 0x0;
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pub const RISCV_OP_M_MULH: u8 = 0x1;
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pub const RISCV_OP_M_MULHSU: u8 = 0x2;
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pub const RISCV_OP_M_MULHU: u8 = 0x3;
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pub const RISCV_OP_M_DIV: u8 = 0x4;
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pub const RISCV_OP_M_DIVU: u8 = 0x5;
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pub const RISCV_OP_M_REM: u8 = 0x6;
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pub const RISCV_OP_M_REMU: u8 = 0x7;
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pub const RISCV_OPW_M_MULW: u8 = 0x0;
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pub const RISCV_OPW_M_DIVW: u8 = 0x4;
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pub const RISCV_OPW_M_DIVUW: u8 = 0x5;
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pub const RISCV_OPW_M_REMW: u8 = 0x6;
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pub const RISCV_OPW_M_REMUW: u8 = 0x7;
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pub const RISCV_FENCE: u8 = 0x0f;
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pub const RISCV_ATOM: u8 = 0x2f;
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pub const RISCV_ATOM_LR: u8 = 0x2;
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pub const RISCV_ATOM_SC: u8 = 0x3;
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pub const RISCV_ATOM_SWAP: u8 = 0x1;
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pub const RISCV_ATOM_ADD: u8 = 0;
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pub const RISCV_ATOM_XOR: u8 = 0x4;
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pub const RISCV_ATOM_AND: u8 = 0xc;
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pub const RISCV_ATOM_OR: u8 = 0x8;
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pub const RISCV_ATOM_MIN: u8 = 0x10;
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pub const RISCV_ATOM_MAX: u8 = 0x14;
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pub const RISCV_ATOM_MINU: u8 = 0x18;
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pub const RISCV_ATOM_MAXU: u8 = 0x1c;
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const names_op: [&str; 8] = ["add", "sll", "slt", "sltu", "xor", "sr", "or", "and"];
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const names_opi: [&str; 8] = ["addi", "slli", "slti", "sltiu", "xori", "slri", "ori", "andi"];
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