Rativel/BurritOS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add tests momery

Browse Source
This commit is contained in:
Quentin Legot 2023-01-18 17:01:48 +01:00
parent b75c7b2d96
commit 66eeb8f2b7
1 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/simulator/machine.rs
View File

@ -308,9 +308,9 @@ impl Machine {
},
RISCV_OP_SLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
machine.int_reg[inst.rd as usize] = 1;
machine.int_reg[inst.rd as usize] = 1;
} else {
machine.int_reg[inst.rd as usize] = 0;
machine.int_reg[inst.rd as usize] = 0;
}
},
RISCV_OP_SLTU => {
@ -410,5 +410,20 @@ impl Machine {
#[cfg(test)]
mod test {
use crate::simulator::machine::Machine;
#[test]
fn test_read_memory() {
let mut m = Machine::_init_machine();
m.main_memory[4] = 43;
m.main_memory[5] = 150;
assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4));
}
fn test_write_memory() {
let mut m = Machine::_init_machine();
Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
assert_eq!(43, m.main_memory[6]);
assert_eq!(150, m.main_memory[7]);
}
}