407 lines
13 KiB
C
407 lines
13 KiB
C
#include "global.h"
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#include "librfu.h"
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static void sio32intr_clock_master(void);
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static void sio32intr_clock_slave(void);
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static u16 handshake_wait(u16 slot);
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static void STWI_set_timer_in_RAM(u8 count);
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static void STWI_stop_timer_in_RAM(void);
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static void STWI_init_slave(void);
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static void Callback_Dummy_M(int reqCommandId, int error, void (*callbackM)());
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static void Callback_Dummy_S(u16 reqCommandId, void (*callbackS)(u16));
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static void Callback_Dummy_ID(void (*callbackId)(void));
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void IntrSIO32(void)
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{
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if (gSTWIStatus->state == 10)
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{
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if (gSTWIStatus->callbackID != NULL)
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Callback_Dummy_ID(gSTWIStatus->callbackID);
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}
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else
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{
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if (gSTWIStatus->msMode == AGB_CLK_MASTER)
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sio32intr_clock_master();
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else
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sio32intr_clock_slave();
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}
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}
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static void sio32intr_clock_master(void)
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{
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u32 regSIODATA32;
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u32 ackLen;
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STWI_set_timer_in_RAM(80);
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regSIODATA32 = REG_SIODATA32;
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if (gSTWIStatus->state == 0) // master send req
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{
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if (regSIODATA32 == 0x80000000)
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{
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if (gSTWIStatus->reqNext <= gSTWIStatus->reqLength)
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{
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REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket->rfuPacket8.data)[gSTWIStatus->reqNext];
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gSTWIStatus->reqNext++;
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}
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else
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{
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gSTWIStatus->state = 1; // master wait ack
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REG_SIODATA32 = 0x80000000;
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}
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}
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else
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{
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STWI_stop_timer_in_RAM();
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STWI_set_timer_in_RAM(130);
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return;
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}
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}
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else if (gSTWIStatus->state == 1) // master wait ack
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{
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if ((regSIODATA32 & 0xFFFF0000) == 0x99660000)
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{
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gSTWIStatus->ackNext = 0;
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((u32*)gSTWIStatus->rxPacket)[gSTWIStatus->ackNext] = regSIODATA32;
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gSTWIStatus->ackNext++;
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gSTWIStatus->ackActiveCommand = regSIODATA32;
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gSTWIStatus->ackLength = ackLen = regSIODATA32 >> 8;
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if ((ackLen = gSTWIStatus->ackLength) >= gSTWIStatus->ackNext)
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{
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gSTWIStatus->state = 2; // master receive ack
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REG_SIODATA32 = 0x80000000;
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}
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else
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{
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gSTWIStatus->state = 3; // master done ack
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}
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}
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else
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{
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STWI_stop_timer_in_RAM();
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STWI_set_timer_in_RAM(130);
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return;
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}
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}
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else if (gSTWIStatus->state == 2) // master receive ack
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{
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((u32*)gSTWIStatus->rxPacket)[gSTWIStatus->ackNext] = regSIODATA32;
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gSTWIStatus->ackNext++;
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if (gSTWIStatus->ackLength < gSTWIStatus->ackNext)
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gSTWIStatus->state = 3; // master done ack
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else
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REG_SIODATA32 = 0x80000000;
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}
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if (handshake_wait(1) == 1)
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return;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_115200_BPS | SIO_MULTI_SD;
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if (handshake_wait(0) == 1)
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return;
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STWI_stop_timer_in_RAM();
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if (gSTWIStatus->state == 3) // master done ack
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{
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if (
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gSTWIStatus->ackActiveCommand == (0x80 | ID_MS_CHANGE_REQ)
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|| gSTWIStatus->ackActiveCommand == (0x80 | ID_DATA_TX_AND_CHANGE_REQ)
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|| gSTWIStatus->ackActiveCommand == (0x80 | ID_UNK35_REQ)
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|| gSTWIStatus->ackActiveCommand == (0x80 | ID_RESUME_RETRANSMIT_AND_CHANGE_REQ)
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)
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{
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gSTWIStatus->msMode = AGB_CLK_SLAVE;
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REG_SIODATA32 = 0x80000000;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS | SIO_ENABLE;
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gSTWIStatus->state = 5; // slave receive req init
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}
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else
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{
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if (gSTWIStatus->ackActiveCommand == 0xEE)
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{
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_115200_BPS;
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gSTWIStatus->state = 4; // error
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gSTWIStatus->error = ERR_REQ_CMD_ACK_REJECTION;
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}
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else
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{
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_115200_BPS;
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gSTWIStatus->state = 4; // error
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}
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}
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gSTWIStatus->sending = 0;
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if (gSTWIStatus->callbackM != NULL)
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Callback_Dummy_M(gSTWIStatus->reqActiveCommand, gSTWIStatus->error, gSTWIStatus->callbackM);
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}
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else
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{
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_115200_BPS;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_115200_BPS | SIO_ENABLE;
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}
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}
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static void sio32intr_clock_slave(void)
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{
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u32 regSIODATA32;
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u32 r0;
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u32 reqLen;
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gSTWIStatus->timerActive = 0;
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STWI_set_timer_in_RAM(100);
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if (handshake_wait(0) == 1)
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return;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS | SIO_MULTI_SD;
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regSIODATA32 = REG_SIODATA32;
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if (gSTWIStatus->state == 5) // slave receive req init
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{
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((u32*)gSTWIStatus->rxPacket)[0] = regSIODATA32;
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gSTWIStatus->reqNext = 1;
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r0 = 0x99660000;
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// variable reuse required
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reqLen = (regSIODATA32 >> 16);
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if (reqLen == (r0 >> 16))
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{
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// only reqLen = regSIODATA32 >> 8 is needed to match, but it looks a bit
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// more consistent when both lines update the variables. Might have been a macro?
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gSTWIStatus->reqLength = reqLen = (regSIODATA32 >> 8);
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gSTWIStatus->reqActiveCommand = reqLen = (regSIODATA32 >> 0);
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if (gSTWIStatus->reqLength == 0)
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{
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if (
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gSTWIStatus->reqActiveCommand == ID_MS_CHANGE_REQ
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|| gSTWIStatus->reqActiveCommand == ID_DATA_READY_AND_CHANGE_REQ
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|| gSTWIStatus->reqActiveCommand == ID_DISCONNECTED_AND_CHANGE_REQ
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|| gSTWIStatus->reqActiveCommand == ID_UNK36_REQ
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)
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{
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gSTWIStatus->ackActiveCommand = gSTWIStatus->reqActiveCommand + 0x80;
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((u32*)gSTWIStatus->txPacket)[0] = 0x99660000 + gSTWIStatus->ackActiveCommand;
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gSTWIStatus->ackLength = 0;
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}
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else
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{
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((u32*)gSTWIStatus->txPacket)[0] = 0x996601EE;
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if (gSTWIStatus->reqActiveCommand >= 0x10 && gSTWIStatus->reqActiveCommand <= 0x3D)
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{
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((u32*)gSTWIStatus->txPacket)[1] = 1;
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}
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else
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{
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((u32*)gSTWIStatus->txPacket)[1] = 2;
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}
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gSTWIStatus->ackLength = 1;
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gSTWIStatus->error = ERR_REQ_CMD_ACK_REJECTION;
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}
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REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket)[0];
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gSTWIStatus->ackNext = 1;
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gSTWIStatus->state = 7; // slave send ack
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}
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else
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{
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REG_SIODATA32 = 0x80000000;
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gSTWIStatus->reqNext = 1;
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gSTWIStatus->state = 6; // slave receive req
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}
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}
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else
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{
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STWI_stop_timer_in_RAM();
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STWI_set_timer_in_RAM(100);
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return;
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}
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}
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else if (gSTWIStatus->state == 6) // slave receive req
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{
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((u32*)gSTWIStatus->rxPacket)[gSTWIStatus->reqNext] = regSIODATA32;
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gSTWIStatus->reqNext++;
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if (gSTWIStatus->reqLength < gSTWIStatus->reqNext)
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{
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if (
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gSTWIStatus->reqActiveCommand == ID_DATA_READY_AND_CHANGE_REQ
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|| gSTWIStatus->reqActiveCommand == ID_DISCONNECTED_AND_CHANGE_REQ
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|| gSTWIStatus->reqActiveCommand == ID_UNK36_REQ
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)
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{
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gSTWIStatus->ackActiveCommand = gSTWIStatus->reqActiveCommand + 0x80;
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((u32*)gSTWIStatus->txPacket)[0] = 0x99660000 | gSTWIStatus->ackActiveCommand;
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gSTWIStatus->ackLength = 0;
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}
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else
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{
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((u32*)gSTWIStatus->txPacket)[0] = 0x996601EE;
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if (gSTWIStatus->reqActiveCommand >= 0x10 && gSTWIStatus->reqActiveCommand <= 0x3D)
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{
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((u32*)gSTWIStatus->txPacket)[1] = 1;
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}
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else
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{
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((u32*)gSTWIStatus->txPacket)[1] = 2;
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}
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gSTWIStatus->ackLength = 1;
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gSTWIStatus->error = ERR_REQ_CMD_ACK_REJECTION;
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}
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REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket)[0];
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gSTWIStatus->ackNext = 1;
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gSTWIStatus->state = 7; // slave send ack
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}
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else
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{
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REG_SIODATA32 = 0x80000000;
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}
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}
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else if (gSTWIStatus->state == 7) // slave send ack
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{
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if (regSIODATA32 == 0x80000000)
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{
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if (gSTWIStatus->ackLength < gSTWIStatus->ackNext)
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{
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gSTWIStatus->state = 8; // slave done ack
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}
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else
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{
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REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket)[gSTWIStatus->ackNext];
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gSTWIStatus->ackNext++;
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}
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}
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else
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{
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STWI_stop_timer_in_RAM();
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STWI_set_timer_in_RAM(100);
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return;
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}
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}
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if (handshake_wait(1) == 1)
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return;
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if (gSTWIStatus->state == 8) // slave done ack
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{
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS;
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STWI_stop_timer_in_RAM();
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if (gSTWIStatus->error == ERR_REQ_CMD_ACK_REJECTION)
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{
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STWI_init_slave();
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if (gSTWIStatus->callbackS != NULL)
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{
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Callback_Dummy_S(0x1EE, gSTWIStatus->callbackS);
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}
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}
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else
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{
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REG_SIODATA32 = 0;
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REG_SIOCNT = 0;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_115200_BPS;
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gSTWIStatus->msMode = AGB_CLK_MASTER;
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gSTWIStatus->state = 0; // master send req
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if (gSTWIStatus->callbackS != NULL)
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{
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Callback_Dummy_S((gSTWIStatus->reqLength << 8) | (gSTWIStatus->reqActiveCommand), gSTWIStatus->callbackS);
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}
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}
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}
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else
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{
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REG_IME = 0;
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if (REG_TM0CNT_H & TIMER_ENABLE)
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{
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if ((REG_TM0CNT_H & 0x03) == TIMER_1CLK)
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{
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while (REG_TM0CNT_L > 0xFF9B);
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}
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else
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{
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while (REG_TM0CNT_L > 0xFFFE);
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}
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}
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS | SIO_ENABLE;
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REG_IME = 1;
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}
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}
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static u16 handshake_wait(u16 slot)
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{
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do
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{
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if ((gSTWIStatus->timerActive & 0xFF) == 1)
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{
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gSTWIStatus->timerActive = 0;
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return 1;
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}
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} while ((REG_SIOCNT & SIO_MULTI_SI) != (slot << SIO_MULTI_SI_SHIFT));
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return 0;
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}
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static void STWI_set_timer_in_RAM(u8 count)
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{
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vu16* regTMCNTL = ®_TMCNT_L(gSTWIStatus->timerSelect);
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vu16* regTMCNTH = ®_TMCNT_H(gSTWIStatus->timerSelect);
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REG_IME = 0;
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switch (count)
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{
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case 50:
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*regTMCNTL = 0xFCCB;
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gSTWIStatus->timerState = 1;
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break;
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case 80:
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*regTMCNTL = 0xFAE0;
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gSTWIStatus->timerState = 2;
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break;
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case 100:
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*regTMCNTL = 0xF996;
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gSTWIStatus->timerState = 3;
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break;
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case 130:
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*regTMCNTL = 0xF7AD;
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gSTWIStatus->timerState = 4;
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break;
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}
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*regTMCNTH = TIMER_ENABLE | TIMER_64CLK | TIMER_256CLK | TIMER_INTR_ENABLE;
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REG_IF = INTR_FLAG_TIMER0 << gSTWIStatus->timerSelect;
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REG_IME = 1;
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}
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static void STWI_stop_timer_in_RAM(void)
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{
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gSTWIStatus->timerState = 0;
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REG_TMCNT_L(gSTWIStatus->timerSelect) = 0;
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REG_TMCNT_H(gSTWIStatus->timerSelect) = 0;
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}
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static void STWI_init_slave(void)
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{
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gSTWIStatus->state = 5; // slave receive req init
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gSTWIStatus->msMode = AGB_CLK_SLAVE;
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gSTWIStatus->reqLength = 0;
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gSTWIStatus->reqNext = 0;
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gSTWIStatus->reqActiveCommand = 0;
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gSTWIStatus->ackLength = 0;
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gSTWIStatus->ackNext = 0;
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gSTWIStatus->ackActiveCommand = 0;
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gSTWIStatus->timerState = 0;
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gSTWIStatus->timerActive = 0;
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gSTWIStatus->error = 0;
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gSTWIStatus->recoveryCount = 0;
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REG_SIOCNT = SIO_INTR_ENABLE | SIO_32BIT_MODE | SIO_57600_BPS | SIO_ENABLE;
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}
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NAKED
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static void Callback_Dummy_M(int reqCommandId, int error, void (*callbackM)())
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{
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asm("bx r2");
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}
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NAKED
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static void Callback_Dummy_S(u16 reqCommandId, void (*callbackS)(u16))
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{
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asm("bx r1");
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}
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NAKED
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static void Callback_Dummy_ID(void (*callbackId)(void))
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{
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asm("bx r0");
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}
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