rubyx/lib/risc/instructions
Torsten 17a7f29b0c define and use syscall_XX registers
rather than use hardcoded r0 etc use syscall_X
change the syscalls and interpreter to use them
later use platform to map from syscall_X to actually used register (like r0 in arm)
2020-03-22 14:31:43 +02:00
..
branch.rb tests for mom check instructions 2019-09-15 19:57:15 +03:00
byte_to_reg.rb remove resolve_to_register 2018-07-16 19:19:49 +03:00
dynamic_jump.rb tests for mom check instructions 2019-09-15 19:57:15 +03:00
function_call.rb fix function call and simple call logic 2018-05-19 12:21:20 +03:00
function_return.rb rename risc_value to register_value 2018-06-29 11:39:07 +03:00
getter.rb rename risc_value to register_value 2018-06-29 11:39:07 +03:00
instruction.rb Unify instruction namings also dirs 2020-03-22 14:31:43 +02:00
label.rb move return address generation to factory 2018-08-29 21:02:49 +03:00
load_constant.rb load constant to create register names with class 2020-03-22 14:31:43 +02:00
load_data.rb Fix div10 and test 2020-03-22 14:31:43 +02:00
operator_instruction.rb make operator_instruction single ass 2020-03-22 14:31:43 +02:00
reg_to_byte.rb remove Risc.resolve_to_index 2018-07-16 19:00:04 +03:00
reg_to_slot.rb codong RegisterSlot with reg and slot 2020-03-22 14:31:43 +02:00
setter.rb fix bug in slot_load and definition 2018-08-19 15:36:51 +03:00
slot_to_reg.rb fix slot_to_reg to allow register indexes 2020-03-22 14:31:43 +02:00
syscall.rb define and use syscall_XX registers 2020-03-22 14:31:43 +02:00
transfer.rb rename risc_value to register_value 2018-06-29 11:39:07 +03:00