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248 Commits

Author SHA1 Message Date
Torsten Ruger
ce79617875 fix the exit sequence 
was returning wrong register (1, not 0)
also saving the message for test, which changes order as the return value destroys the message
 2018-06-19 19:52:06 +03:00
Torsten Ruger
db459fcd3d fix label loading in arm 
was still loading the integer address
instead of the return address's address
Hello World working
 2018-06-19 17:35:00 +03:00
Torsten Ruger
956c2ebe54 make arm use branch_lsteners 2018-06-19 10:51:03 +03:00
Torsten Ruger
9fc7f9b528 fix arm write syscall 2018-06-19 10:49:53 +03:00
Torsten Ruger
3298651238 split create_binary into two phases 
Which gives instructions a chance to check everything
and in Arms case check the constant loads/ instruction adding
So that during assembly no more change happens (and we don't have to reassemble)
 2018-06-17 13:53:17 +03:00
Torsten Ruger
ad3040a846 add position_chaning to event interface 
by reacting to the change _before it happens, we can move any BinaryCode out of the way

So when Instruction are inserted and code gets inserted, we don't need to set up the correct listener explicitly (which is tricky across mathods and changing chains), but instead just move anything that is in the way along
 2018-06-09 08:10:41 +03:00
Torsten Ruger
c22aff4c4f start on insertion events and handling 2018-06-06 10:00:07 +03:00
Torsten Ruger
4ab6d62acf small arm fixes etc 2018-06-06 00:53:41 +03:00
Torsten Ruger
d7b3368b28 fix some pesty errors 
need to fix instruction overlap beofre interpreter starts again
 2018-06-05 19:05:12 +03:00
Torsten Ruger
8d953a619f propagate instruction positions 
still overlapping onto binaries, but a start
 2018-06-05 18:11:25 +03:00
Torsten Ruger
c2d450f779 fold position module and object position 
simpler that way, aslo code is moving to listners
 2018-06-02 21:59:41 +03:00
Torsten Ruger
24f6e30b54 start on redoing instruction positions 
using insruction listeners (wip)
 2018-06-02 21:20:15 +03:00
Torsten Ruger
0e155315aa movs is not allowed into pc 
Illegal instruction it says
Otherwise the status update is nice (for branches) and we’ll keep
 2018-05-31 14:03:25 +03:00
Torsten Ruger
67100a3ef8 write adjusted address 
and rename integer to address in label
1k hurray
 2018-05-31 00:07:58 +03:00
Torsten Ruger
0dc89c772a get the label int to work consistently 
still need to use it in the return
 2018-05-30 10:54:18 +03:00
Torsten Ruger
074ec34659 wip, fixed some label, need more fixing 2018-05-30 10:29:38 +03:00
Torsten Ruger
8322fca7b3 give labels an integer that will end up being the position at runtime 
Since integers are first class objects, we need to use an integer object
as the return address. The actual address can not be stored in an
instance variable since it is not an object.
The address is unique to the label and never changes after positioning
(using the int is next up)
 2018-05-29 20:26:00 +03:00
Torsten Ruger
b81d9565de fix binary code offset when calling 
in other words, remember the arm pipeline being 8
 2018-05-29 17:03:20 +03:00
Torsten Ruger
6f0fad0957 dragging the extra through resets 
as the binary the instruction is in may change when repositioning
 2018-05-25 19:04:48 +03:00
Torsten Ruger
3c00239f36 another million index fixes 2018-05-14 15:17:04 +03:00
Torsten Ruger
232fe67c09 introduce platform to abstract cpu and load address 2018-05-12 18:32:10 +03:00
Torsten Ruger
6a1528e75a Fix instruction resetting 
which happens on insert of a new instruction
 2018-05-08 20:53:48 +03:00
Torsten Ruger
7ca7e92dda remove link exception class 2018-05-08 20:22:04 +03:00
Torsten Ruger
ce3cc72f9e move all position setting into position 
Position and subclasses handle the logic, external to
the classes, so it can be swapped out later
(at runtime positions can’t change)
 2018-05-07 22:30:43 +03:00
Torsten Ruger
68fb9b1bdc rename Position get/set 2018-05-06 20:04:02 +03:00
Torsten Ruger
e89c4d1ce1 pass binary that arm instruction belongs to in 
at least to first. repositioning and stuff next
 2018-05-06 19:56:36 +03:00
Torsten Ruger
6b7e1e3932 remove link exception raise 
need to fix move logic next
 2018-05-05 23:55:50 +03:00
Torsten Ruger
d65a982454 start by moving positioned(module) to position(class) 2018-05-05 19:47:18 +03:00
Torsten Ruger
43d5521cfc debugging positions 2018-05-05 19:32:01 +03:00
Torsten Ruger
1acd231a33 debugging binaries, initial jump issues 2018-04-30 13:28:55 +03:00
Torsten Ruger
30ca70e042 remove extra instruction and use next instead 
was messing with binary writing as the assumption of 1 word writes is
baked in
 2018-04-03 14:46:07 +03:00
Torsten Ruger
beb487eb09 minor fixes 2018-04-02 19:31:08 +03:00
Torsten Ruger
a2173645b3 remove the :int shorthand 2018-03-31 19:17:55 +03:00
Torsten Ruger
6e941ebcb7 introduce load_data instruction 
which just loads data to a register (used internally)
as opposed to integers, which are objects
 2018-03-31 12:38:30 +03:00
Torsten Ruger
1956f18faa add an integer plus 
not correctly handling integer objects yet
 2018-03-30 17:09:02 +03:00
Torsten Ruger
7cf253ad9c change assembler to write binary code objects 
also all debug in hex
 2018-03-29 12:16:27 +03:00
Torsten Ruger
606e3f8cb3 fix calling to binaries 
used to be to the method, but we assemble the method to its own
position.
Throw in a test for binary calling
 2018-03-28 13:00:03 +03:00
Torsten Ruger
7493d738e1 have to translate the labels 
and use binary as function call target
(because we don’t have the translated label)
 2018-03-28 12:50:07 +03:00
Torsten Ruger
2e57674008 remove io.write_unsigned_8 
and replace with write_unsigned_32, so that is the only used
method from the stream
Next up, replace the actual “stream” with a binary code writer
 2018-03-27 19:37:52 +03:00
Torsten Ruger
c5b3c3f106 give arm own instruction base class back 2018-03-26 20:04:39 +03:00
Torsten Ruger
294f4d988f automatically create binary once cpu instructions are there 2018-03-26 19:42:15 +03:00
Torsten Ruger
279fdcc1e2 really translate risc - cpu/arm 
also labels.
Actual translation/assembly is much cleaner
 2018-03-25 19:38:59 +03:00
Torsten Ruger
8cee2db1d1 return just gets the register (no more offset) 
use mov instead
 2018-03-24 18:32:53 +02:00
Torsten Ruger
b4489b1093 rename RiscTransfer to Transfer 2018-03-21 15:48:04 +05:30
Torsten Ruger
99ced4369a adding Tue False and Nil Class to Parfait 
and boot
 2018-03-19 21:18:56 +05:30
Torsten Ruger
f7aac1d1a4 polish docs 
and a bit of code style
 2018-03-11 16:11:15 +05:30
Torsten Ruger
aa79e41d1c rename register to risc 
seems to fit the layer much better as we really have a very reduced
instruction set
 2017-01-19 09:02:29 +02:00
Torsten Ruger
0397d4064d fix all positioned uses as helper (not included anymore) 2017-01-01 21:52:55 +02:00
Torsten Ruger
b094bcc64f rename unit and sint to human readable forms 2016-12-31 18:45:22 +02:00
Torsten Ruger
8aae8f7425 disabling failing test for now 
have to add more test and code climate will show where
 2016-12-29 21:24:11 +02:00