Torsten Ruger
65d57c8c7c
removing unconditional
...
just Branch is fine
2018-04-02 19:30:34 +03:00
Torsten Ruger
6e941ebcb7
introduce load_data instruction
...
which just loads data to a register (used internally)
as opposed to integers, which are objects
2018-03-31 12:38:30 +03:00
Torsten Ruger
1956f18faa
add an integer plus
...
not correctly handling integer objects yet
2018-03-30 17:09:02 +03:00
Torsten Ruger
4253d7a6b9
move assembly from assembler to machine
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id now called position
2018-03-27 18:47:39 +03:00
Torsten Ruger
4cc1d8455e
fix util namespace
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and instruction move ripples
2018-03-26 20:05:30 +03:00
Torsten Ruger
e61ef93943
cleanup
2018-03-26 19:17:30 +03:00
Torsten Ruger
b24b65520d
remove all that label stuff
...
left over after rewrite from blocks to linked list
2018-03-26 14:54:41 +03:00
Torsten Ruger
231025389a
little cleanup
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code climate inspired
2018-03-26 14:15:48 +03:00
Torsten Ruger
279fdcc1e2
really translate risc - cpu/arm
...
also labels.
Actual translation/assembly is much cleaner
2018-03-25 19:38:59 +03:00
Torsten Ruger
de7e02b0b8
remove IsSame branch from risc
...
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
Torsten Ruger
6a538624c5
remove NotSame from risc
...
instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
Torsten Ruger
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
Torsten Ruger
9932d0bf33
add source to the to_s
2018-03-22 18:38:19 +02:00
Torsten Ruger
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
Torsten Ruger
b5ef929c9c
add method to risc function call
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just so we still know at compile time
2018-03-21 19:05:53 +05:30
Torsten Ruger
fcbdba4804
simplify method entry exit codes
...
Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
Torsten Ruger
61a801b00c
Return to_risc
...
remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
Torsten Ruger
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
Torsten Ruger
fa797f722d
to_risc for NotSameCheck
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which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
Torsten Ruger
d98e55907e
first go at translating DynamicCall to risc
2018-03-21 11:51:10 +05:30
Torsten Ruger
77084dc894
fix unconditional jump
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and affected tests
2018-03-20 22:05:09 +05:30
Torsten Ruger
c8980595a3
start to test if
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truth check is only half done
2018-03-19 21:20:11 +05:30
Torsten Ruger
cddc25a595
fixing tests for shifting constants into slots
2018-03-17 21:15:38 +05:30
Torsten Ruger
79b4b07ac4
style
2018-03-14 17:39:49 +05:30
Torsten Ruger
aa79e41d1c
rename register to risc
...
seems to fit the layer much better as we really have a very reduced
instruction set
2017-01-19 09:02:29 +02:00
