Torsten Ruger
3090ccffea
keep risc and cpu instructions separate in method
...
that overwriting was a bit of thorn
2018-03-25 19:33:50 +03:00
Torsten Ruger
a50368c3aa
assembler will need redoing somewhat
...
with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
Torsten Ruger
82ab8ac4d3
add data objects
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marker class (may change) to be able to check access
2018-03-25 18:22:02 +03:00
Torsten Ruger
bc4d4b428a
change boot to new hash syntax
2018-03-25 13:27:15 +03:00
Torsten Ruger
de7e02b0b8
remove IsSame branch from risc
...
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
Torsten Ruger
a407601f5c
fix tests from NotSame removal
2018-03-24 18:33:19 +02:00
Torsten Ruger
8cee2db1d1
return just gets the register (no more offset)
...
use mov instead
2018-03-24 18:32:53 +02:00
Torsten Ruger
ad3e73d931
start on dynamic call test
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fix cache entry being not loaded
test incomplete because of missing resolve_method
2018-03-24 17:55:01 +02:00
Torsten Ruger
6a538624c5
remove NotSame from risc
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instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
Torsten Ruger
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
Torsten Ruger
3ceb2c2f69
fix div10 return sequence
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did not return at all before
2018-03-24 16:51:26 +02:00
Torsten Ruger
267237b776
fix init method message setup
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was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
Torsten Ruger
65d3d5f1c9
fix tests from interpreter load change
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loading values, not Constants
2018-03-24 12:24:53 +02:00
Torsten Ruger
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
Torsten Ruger
30d2cd3af7
fix test ripples from changing return sequence
2018-03-23 20:04:29 +02:00
Torsten Ruger
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
Torsten Ruger
6721153456
fix return sequence
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logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
2018-03-23 18:58:42 +02:00
Torsten Ruger
a306c464b7
start using tmp registers at 1
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which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
Torsten Ruger
472b1a638a
add register logging and fix function return
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return semantics used to be different, now only register is given
2018-03-23 18:56:38 +02:00
Torsten Ruger
b4a18bc59b
mostly brackets and formatting
2018-03-23 18:55:23 +02:00
Torsten Ruger
c51e593335
test return in interpreter
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passes but does not return. dodgy
2018-03-23 11:36:20 +02:00
Torsten Ruger
f46c4d148e
more return testing
2018-03-23 11:21:41 +02:00
Torsten Ruger
55832315eb
more fix for multilevel constant load
...
was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
Torsten Ruger
34903829ca
fix interpreter test harness and start testing
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interpreter on debug for now
2018-03-22 18:54:40 +02:00
Torsten Ruger
e505856af7
fix multi level right slot load
...
was done for left, but forgotten for right
2018-03-22 18:54:07 +02:00
Torsten Ruger
6e901e1718
allow setting the source for slot loads
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so we can track more exactly which instruction created the risc
2018-03-22 18:45:03 +02:00
Torsten Ruger
9932d0bf33
add source to the to_s
2018-03-22 18:38:19 +02:00
Torsten Ruger
19afc376f4
fix local name being string (not symbol)
2018-03-22 21:08:13 +05:30
Torsten Ruger
769fd71a3d
fix redefining typed methods
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as happens for predefined Space.main
2018-03-22 21:06:22 +05:30
Torsten Ruger
02c12996b3
return test for risc
2018-03-22 02:38:41 +05:30
Torsten Ruger
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
Torsten Ruger
01151b4ba7
make continue labels unique
2018-03-21 22:05:51 +05:30
Torsten Ruger
e0dd4e0ad7
test dynamic call
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made cache labels unique
2018-03-21 21:58:43 +05:30
Torsten Ruger
f424e58715
finish the simple call
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moving jump address
2018-03-21 19:29:00 +05:30
Torsten Ruger
49880267bb
start to test call
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as per tdd noticing logic errors, have to swap message out
2018-03-21 19:20:51 +05:30
Torsten Ruger
b5ef929c9c
add method to risc function call
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just so we still know at compile time
2018-03-21 19:05:53 +05:30
Torsten Ruger
a9196e9cd6
implement simple_calls to_risc
2018-03-21 18:54:42 +05:30
Torsten Ruger
71c59e5bc0
remove calls from tests that don't test call
2018-03-21 16:11:57 +05:30
Torsten Ruger
fcbdba4804
simplify method entry exit codes
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Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
Torsten Ruger
61a801b00c
Return to_risc
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remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
Torsten Ruger
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
Torsten Ruger
fa797f722d
to_risc for NotSameCheck
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which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
Torsten Ruger
12c71fa394
first go at message setups translation to risc
...
simplest possible implementation, ie the method and next_messages are
loaded many times.
But the layer design shines, it’s easy to understand
2018-03-21 12:20:55 +05:30
Torsten Ruger
b99fdc3425
rename jump label
2018-03-21 11:52:53 +05:30
Torsten Ruger
d98e55907e
first go at translating DynamicCall to risc
2018-03-21 11:51:10 +05:30
Torsten Ruger
d9ce295b89
fix all tests from removing the receiver load
2018-03-20 23:31:42 +05:30
Torsten Ruger
48485477c2
implement one more depth for slot_load
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soon time to make some loop
fix offset with array / object layout difference
2018-03-20 23:31:20 +05:30
Torsten Ruger
8dc0950980
implement ArgumentTransfer
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also unite with the receiver which was handled incorrectly
(left as a Vool constant)
2018-03-20 22:31:39 +05:30
Torsten Ruger
77084dc894
fix unconditional jump
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and affected tests
2018-03-20 22:05:09 +05:30
Torsten Ruger
c12830ee6d
simple while risc conversion test
2018-03-20 16:32:07 +05:30
