Torsten Ruger
5eee79719d
reenable now working tests
2018-03-28 13:04:25 +03:00
Torsten Ruger
606e3f8cb3
fix calling to binaries
...
used to be to the method, but we assemble the method to its own
position.
Throw in a test for binary calling
2018-03-28 13:00:03 +03:00
Torsten Ruger
7493d738e1
have to translate the labels
...
and use binary as function call target
(because we don’t have the translated label)
2018-03-28 12:50:07 +03:00
Torsten Ruger
85ddf53429
create methods with binaries and extend them later
...
Binary is new jump target for function call
2018-03-28 12:49:17 +03:00
Torsten Ruger
105e8f7092
some better and some missing arm test
...
for the exceptional case
2018-03-28 12:16:28 +03:00
Torsten Ruger
fcb7f652eb
found the culprit
2018-03-28 11:37:17 +03:00
Torsten Ruger
500851d246
start on new binary creation process
...
now writing into BinaryCode instead of stream
also in the risc layer, not arm, for reusability
2018-03-27 20:47:41 +03:00
Torsten Ruger
2e57674008
remove io.write_unsigned_8
...
and replace with write_unsigned_32, so that is the only used
method from the stream
Next up, replace the actual “stream” with a binary code writer
2018-03-27 19:37:52 +03:00
Torsten Ruger
4069397fca
don't collect labels anymore
...
don’t need, use binary code as the methods jump point
2018-03-27 19:06:16 +03:00
Torsten Ruger
4253d7a6b9
move assembly from assembler to machine
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id now called position
2018-03-27 18:47:39 +03:00
Torsten Ruger
4cc1d8455e
fix util namespace
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and instruction move ripples
2018-03-26 20:05:30 +03:00
Torsten Ruger
c5b3c3f106
give arm own instruction base class back
2018-03-26 20:04:39 +03:00
Torsten Ruger
4a26bec0f1
move eventable to util and rename common to util
2018-03-26 19:46:38 +03:00
Torsten Ruger
730197fbed
organise tests to where they belong
2018-03-26 19:43:03 +03:00
Torsten Ruger
e8f449bc65
reuse translator in machine and clean up api
2018-03-26 19:42:40 +03:00
Torsten Ruger
294f4d988f
automatically create binary once cpu instructions are there
2018-03-26 19:42:15 +03:00
Torsten Ruger
3fcb4b74c7
fix binary code set_char bug
2018-03-26 19:41:30 +03:00
Torsten Ruger
e61ef93943
cleanup
2018-03-26 19:17:30 +03:00
Torsten Ruger
46a5eefbd4
reorder methods as they are called
2018-03-26 18:18:25 +03:00
Torsten Ruger
a9d5e144ca
get/set word for binary code
2018-03-26 18:14:52 +03:00
Torsten Ruger
25c5b6dbbd
do or do not, there is not try
2018-03-26 18:14:39 +03:00
Torsten Ruger
b24b65520d
remove all that label stuff
...
left over after rewrite from blocks to linked list
2018-03-26 14:54:41 +03:00
Torsten Ruger
1e21177b35
just keep binary code payload at 13 for now
...
there is an extra in there at the last of the last, but ok
2018-03-26 14:37:55 +03:00
Torsten Ruger
231025389a
little cleanup
...
code climate inspired
2018-03-26 14:15:48 +03:00
Torsten Ruger
60617ca632
some binary code tests
2018-03-26 14:04:13 +03:00
Torsten Ruger
633e99466d
start to debug
2018-03-26 13:43:26 +03:00
Torsten Ruger
865a116f47
small assembler fix
2018-03-25 20:02:51 +03:00
Torsten Ruger
279fdcc1e2
really translate risc - cpu/arm
...
also labels.
Actual translation/assembly is much cleaner
2018-03-25 19:38:59 +03:00
Torsten Ruger
eb7713a9f3
remove method_compiler init method
...
as init is really just adding a label it is done in the method
(thus mixing the levels, “polluting” parfait with risc, but there must
be change coming that way anyway)
2018-03-25 19:37:51 +03:00
Torsten Ruger
3bd23cee28
also separate risc and cpu inits for the machine
...
interpreter works on risc, but assembler off cpu
2018-03-25 19:36:00 +03:00
Torsten Ruger
3090ccffea
keep risc and cpu instructions separate in method
...
that overwriting was a bit of thorn
2018-03-25 19:33:50 +03:00
Torsten Ruger
a50368c3aa
assembler will need redoing somewhat
...
with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
Torsten Ruger
82ab8ac4d3
add data objects
...
marker class (may change) to be able to check access
2018-03-25 18:22:02 +03:00
Torsten Ruger
bc4d4b428a
change boot to new hash syntax
2018-03-25 13:27:15 +03:00
Torsten Ruger
de7e02b0b8
remove IsSame branch from risc
...
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
Torsten Ruger
a407601f5c
fix tests from NotSame removal
2018-03-24 18:33:19 +02:00
Torsten Ruger
8cee2db1d1
return just gets the register (no more offset)
...
use mov instead
2018-03-24 18:32:53 +02:00
Torsten Ruger
ad3e73d931
start on dynamic call test
...
fix cache entry being not loaded
test incomplete because of missing resolve_method
2018-03-24 17:55:01 +02:00
Torsten Ruger
6a538624c5
remove NotSame from risc
...
instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
Torsten Ruger
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
Torsten Ruger
3ceb2c2f69
fix div10 return sequence
...
did not return at all before
2018-03-24 16:51:26 +02:00
Torsten Ruger
267237b776
fix init method message setup
...
was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
Torsten Ruger
65d3d5f1c9
fix tests from interpreter load change
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loading values, not Constants
2018-03-24 12:24:53 +02:00
Torsten Ruger
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
Torsten Ruger
30d2cd3af7
fix test ripples from changing return sequence
2018-03-23 20:04:29 +02:00
Torsten Ruger
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
Torsten Ruger
6721153456
fix return sequence
...
logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
2018-03-23 18:58:42 +02:00
Torsten Ruger
a306c464b7
start using tmp registers at 1
...
which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
Torsten Ruger
472b1a638a
add register logging and fix function return
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return semantics used to be different, now only register is given
2018-03-23 18:56:38 +02:00
Torsten Ruger
b4a18bc59b
mostly brackets and formatting
2018-03-23 18:55:23 +02:00
