Torsten Ruger
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bbb7dbef75
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First part of int allocation
implemented allocate_int
instead of add_new_int
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2018-11-21 11:12:39 +02:00 |
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Torsten Ruger
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f5c284b3a0
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bring the blocks down to mom level
reusing message_setup, but adding yield specific instructions
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2018-07-24 11:35:49 +03:00 |
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Torsten Ruger
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e099014d63
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fix dunamic jump in interpreter and misc
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2018-07-03 19:15:36 +03:00 |
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Torsten Ruger
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046617f8dc
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add branch listener functionaliy
have to store the branches and loop again as labels
dont neccessarily have positions yet
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2018-06-17 22:25:38 +03:00 |
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Torsten Ruger
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3cc9175efa
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start BranchListener
but on hold, since it needs positions before we have them
Must create them during collection phase
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2018-06-14 21:29:34 +03:00 |
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Torsten Ruger
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6f0fad0957
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dragging the extra through resets
as the binary the instruction is in may change when repositioning
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2018-05-25 19:04:48 +03:00 |
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Torsten Ruger
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65d57c8c7c
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removing unconditional
just Branch is fine
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2018-04-02 19:30:34 +03:00 |
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Torsten Ruger
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b24b65520d
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remove all that label stuff
left over after rewrite from blocks to linked list
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2018-03-26 14:54:41 +03:00 |
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Torsten Ruger
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de7e02b0b8
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remove IsSame branch from risc
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
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2018-03-24 18:54:36 +02:00 |
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Torsten Ruger
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6a538624c5
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remove NotSame from risc
instead use a - b and then isZero
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2018-03-24 17:54:15 +02:00 |
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Torsten Ruger
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9932d0bf33
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add source to the to_s
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2018-03-22 18:38:19 +02:00 |
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Torsten Ruger
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fa797f722d
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to_risc for NotSameCheck
which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
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2018-03-21 12:38:28 +05:30 |
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Torsten Ruger
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d98e55907e
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first go at translating DynamicCall to risc
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2018-03-21 11:51:10 +05:30 |
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Torsten Ruger
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77084dc894
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fix unconditional jump
and affected tests
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2018-03-20 22:05:09 +05:30 |
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Torsten Ruger
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c8980595a3
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start to test if
truth check is only half done
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2018-03-19 21:20:11 +05:30 |
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Torsten Ruger
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aa79e41d1c
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rename register to risc
seems to fit the layer much better as we really have a very reduced
instruction set
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2017-01-19 09:02:29 +02:00 |
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