500851d246
start on new binary creation process
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now writing into BinaryCode instead of stream
also in the risc layer, not arm, for reusability
2018-03-27 20:47:41 +03:00
2e57674008
remove io.write_unsigned_8
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and replace with write_unsigned_32, so that is the only used
method from the stream
Next up, replace the actual “stream” with a binary code writer
2018-03-27 19:37:52 +03:00
4069397fca
don't collect labels anymore
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don’t need, use binary code as the methods jump point
2018-03-27 19:06:16 +03:00
4253d7a6b9
move assembly from assembler to machine
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id now called position
2018-03-27 18:47:39 +03:00
4cc1d8455e
fix util namespace
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and instruction move ripples
2018-03-26 20:05:30 +03:00
c5b3c3f106
give arm own instruction base class back
2018-03-26 20:04:39 +03:00
4a26bec0f1
move eventable to util and rename common to util
2018-03-26 19:46:38 +03:00
e8f449bc65
reuse translator in machine and clean up api
2018-03-26 19:42:40 +03:00
294f4d988f
automatically create binary once cpu instructions are there
2018-03-26 19:42:15 +03:00
3fcb4b74c7
fix binary code set_char bug
2018-03-26 19:41:30 +03:00
e61ef93943
cleanup
2018-03-26 19:17:30 +03:00
46a5eefbd4
reorder methods as they are called
2018-03-26 18:18:25 +03:00
a9d5e144ca
get/set word for binary code
2018-03-26 18:14:52 +03:00
25c5b6dbbd
do or do not, there is not try
2018-03-26 18:14:39 +03:00
b24b65520d
remove all that label stuff
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left over after rewrite from blocks to linked list
2018-03-26 14:54:41 +03:00
1e21177b35
just keep binary code payload at 13 for now
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there is an extra in there at the last of the last, but ok
2018-03-26 14:37:55 +03:00
231025389a
little cleanup
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code climate inspired
2018-03-26 14:15:48 +03:00
60617ca632
some binary code tests
2018-03-26 14:04:13 +03:00
633e99466d
start to debug
2018-03-26 13:43:26 +03:00
865a116f47
small assembler fix
2018-03-25 20:02:51 +03:00
279fdcc1e2
really translate risc - cpu/arm
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also labels.
Actual translation/assembly is much cleaner
2018-03-25 19:38:59 +03:00
eb7713a9f3
remove method_compiler init method
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as init is really just adding a label it is done in the method
(thus mixing the levels, “polluting” parfait with risc, but there must
be change coming that way anyway)
2018-03-25 19:37:51 +03:00
3bd23cee28
also separate risc and cpu inits for the machine
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interpreter works on risc, but assembler off cpu
2018-03-25 19:36:00 +03:00
3090ccffea
keep risc and cpu instructions separate in method
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that overwriting was a bit of thorn
2018-03-25 19:33:50 +03:00
a50368c3aa
assembler will need redoing somewhat
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with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
82ab8ac4d3
add data objects
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marker class (may change) to be able to check access
2018-03-25 18:22:02 +03:00
bc4d4b428a
change boot to new hash syntax
2018-03-25 13:27:15 +03:00
de7e02b0b8
remove IsSame branch from risc
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mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
8cee2db1d1
return just gets the register (no more offset)
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use mov instead
2018-03-24 18:32:53 +02:00
ad3e73d931
start on dynamic call test
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fix cache entry being not loaded
test incomplete because of missing resolve_method
2018-03-24 17:55:01 +02:00
6a538624c5
remove NotSame from risc
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instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
3ceb2c2f69
fix div10 return sequence
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did not return at all before
2018-03-24 16:51:26 +02:00
267237b776
fix init method message setup
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was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
6721153456
fix return sequence
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logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
2018-03-23 18:58:42 +02:00
a306c464b7
start using tmp registers at 1
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which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
472b1a638a
add register logging and fix function return
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return semantics used to be different, now only register is given
2018-03-23 18:56:38 +02:00
b4a18bc59b
mostly brackets and formatting
2018-03-23 18:55:23 +02:00
55832315eb
more fix for multilevel constant load
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was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
34903829ca
fix interpreter test harness and start testing
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interpreter on debug for now
2018-03-22 18:54:40 +02:00
e505856af7
fix multi level right slot load
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was done for left, but forgotten for right
2018-03-22 18:54:07 +02:00
6e901e1718
allow setting the source for slot loads
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so we can track more exactly which instruction created the risc
2018-03-22 18:45:03 +02:00
9932d0bf33
add source to the to_s
2018-03-22 18:38:19 +02:00
19afc376f4
fix local name being string (not symbol)
2018-03-22 21:08:13 +05:30
769fd71a3d
fix redefining typed methods
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as happens for predefined Space.main
2018-03-22 21:06:22 +05:30
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
01151b4ba7
make continue labels unique
2018-03-21 22:05:51 +05:30
e0dd4e0ad7
test dynamic call
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made cache labels unique
2018-03-21 21:58:43 +05:30
