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1595 Commits

Author SHA1 Message Date
Torsten Ruger
e8f449bc65 reuse translator in machine and clean up api 2018-03-26 19:42:40 +03:00
Torsten Ruger
294f4d988f automatically create binary once cpu instructions are there 2018-03-26 19:42:15 +03:00
Torsten Ruger
3fcb4b74c7 fix binary code set_char bug 2018-03-26 19:41:30 +03:00
Torsten Ruger
e61ef93943 cleanup 2018-03-26 19:17:30 +03:00
Torsten Ruger
46a5eefbd4 reorder methods as they are called 2018-03-26 18:18:25 +03:00
Torsten Ruger
a9d5e144ca get/set word for binary code 2018-03-26 18:14:52 +03:00
Torsten Ruger
25c5b6dbbd do or do not, there is not try 2018-03-26 18:14:39 +03:00
Torsten Ruger
b24b65520d remove all that label stuff 
left over after rewrite from blocks to linked list
 2018-03-26 14:54:41 +03:00
Torsten Ruger
1e21177b35 just keep binary code payload at 13 for now 
there is an extra in there at the last of the last, but ok
 2018-03-26 14:37:55 +03:00
Torsten Ruger
231025389a little cleanup 
code climate inspired
 2018-03-26 14:15:48 +03:00
Torsten Ruger
60617ca632 some binary code tests 2018-03-26 14:04:13 +03:00
Torsten Ruger
633e99466d start to debug 2018-03-26 13:43:26 +03:00
Torsten Ruger
865a116f47 small assembler fix 2018-03-25 20:02:51 +03:00
Torsten Ruger
279fdcc1e2 really translate risc - cpu/arm 
also labels.
Actual translation/assembly is much cleaner
 2018-03-25 19:38:59 +03:00
Torsten Ruger
eb7713a9f3 remove method_compiler init method 
as init is really just adding a label it is done in the method
 (thus mixing the levels, “polluting” parfait with risc, but there must
be change coming that way anyway)
 2018-03-25 19:37:51 +03:00
Torsten Ruger
3bd23cee28 also separate risc and cpu inits for the machine 
interpreter works on risc, but assembler off cpu
 2018-03-25 19:36:00 +03:00
Torsten Ruger
3090ccffea keep risc and cpu instructions separate in method 
that overwriting was a bit of thorn
 2018-03-25 19:33:50 +03:00
Torsten Ruger
a50368c3aa assembler will need redoing somewhat 
with own data objects, we can assemble into them first
then write
may also store cpu instructions
 2018-03-25 18:23:00 +03:00
Torsten Ruger
82ab8ac4d3 add data objects 
marker class (may change) to be able to check access
 2018-03-25 18:22:02 +03:00
Torsten Ruger
bc4d4b428a change boot to new hash syntax 2018-03-25 13:27:15 +03:00
Torsten Ruger
de7e02b0b8 remove IsSame branch from risc 
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
 2018-03-24 18:54:36 +02:00
Torsten Ruger
8cee2db1d1 return just gets the register (no more offset) 
use mov instead
 2018-03-24 18:32:53 +02:00
Torsten Ruger
ad3e73d931 start on dynamic call test 
fix cache entry being not loaded
test incomplete because of missing resolve_method
 2018-03-24 17:55:01 +02:00
Torsten Ruger
6a538624c5 remove NotSame from risc 
instead use a - b and then  isZero
 2018-03-24 17:54:15 +02:00
Torsten Ruger
793fa313a5 change operators to symbols 2018-03-24 17:53:27 +02:00
Torsten Ruger
3ceb2c2f69 fix div10 return sequence 
did not return at all before
 2018-03-24 16:51:26 +02:00
Torsten Ruger
267237b776 fix init method message setup 
was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
 2018-03-24 15:59:54 +02:00
Torsten Ruger
2c137e8c97 div10 test for interpreter 2018-03-24 12:21:46 +02:00
Torsten Ruger
0f183b3a74 fix value return and test 
slot load was wrong way around
 2018-03-23 20:02:17 +02:00
Torsten Ruger
6721153456 fix return sequence 
logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
 2018-03-23 18:58:42 +02:00
Torsten Ruger
a306c464b7 start using tmp registers at 1 
which used to be reserved for the next message
 2018-03-23 18:57:16 +02:00
Torsten Ruger
472b1a638a add register logging and fix function return 
return semantics used to be different, now only register is given
 2018-03-23 18:56:38 +02:00
Torsten Ruger
b4a18bc59b mostly brackets and formatting 2018-03-23 18:55:23 +02:00
Torsten Ruger
55832315eb more fix for multilevel constant load 
was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
 2018-03-22 19:14:22 +02:00
Torsten Ruger
34903829ca fix interpreter test harness and start testing 
interpreter on debug for now
 2018-03-22 18:54:40 +02:00
Torsten Ruger
e505856af7 fix multi level right slot load 
was done for left, but forgotten for right
 2018-03-22 18:54:07 +02:00
Torsten Ruger
6e901e1718 allow setting the source for slot loads 
so we can track more exactly which instruction created the risc
 2018-03-22 18:45:03 +02:00
Torsten Ruger
9932d0bf33 add source to the to_s 2018-03-22 18:38:19 +02:00
Torsten Ruger
19afc376f4 fix local name being string (not symbol) 2018-03-22 21:08:13 +05:30
Torsten Ruger
769fd71a3d fix redefining typed methods 
as happens for predefined Space.main
 2018-03-22 21:06:22 +05:30
Torsten Ruger
ca3bf6acfa fix constants being passed down 2018-03-22 02:38:06 +05:30
Torsten Ruger
01151b4ba7 make continue labels unique 2018-03-21 22:05:51 +05:30
Torsten Ruger
e0dd4e0ad7 test dynamic call 
made cache labels unique
 2018-03-21 21:58:43 +05:30
Torsten Ruger
f424e58715 finish the simple call 
moving jump address
 2018-03-21 19:29:00 +05:30
Torsten Ruger
49880267bb start to test call 
as per tdd noticing logic errors, have to swap message out
 2018-03-21 19:20:51 +05:30
Torsten Ruger
b5ef929c9c add method to risc function call 
just so we still know at compile time
 2018-03-21 19:05:53 +05:30
Torsten Ruger
a9196e9cd6 implement simple_calls to_risc 2018-03-21 18:54:42 +05:30
Torsten Ruger
fcbdba4804 simplify method entry exit codes 
Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
 2018-03-21 16:02:46 +05:30
Torsten Ruger
61a801b00c Return to_risc 
remove the index from FunctionReturn, just jump to the register address
 2018-03-21 15:48:50 +05:30
Torsten Ruger
b4489b1093 rename RiscTransfer to Transfer 2018-03-21 15:48:04 +05:30
Torsten Ruger
fa797f722d to_risc for NotSameCheck 
which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
 2018-03-21 12:38:28 +05:30
Torsten Ruger
12c71fa394 first go at message setups translation to risc 
simplest possible implementation, ie the method and next_messages are
loaded many times.

But the layer design shines, it’s easy to understand
 2018-03-21 12:20:55 +05:30
Torsten Ruger
b99fdc3425 rename jump label 2018-03-21 11:52:53 +05:30
Torsten Ruger
d98e55907e first go at translating DynamicCall to risc 2018-03-21 11:51:10 +05:30
Torsten Ruger
48485477c2 implement one more depth for slot_load 
soon time to make some loop
fix offset with array / object layout difference
 2018-03-20 23:31:20 +05:30
Torsten Ruger
8dc0950980 implement ArgumentTransfer 
also unite with the receiver which was handled incorrectly
(left as a Vool constant)
 2018-03-20 22:31:39 +05:30
Torsten Ruger
77084dc894 fix unconditional jump 
and affected tests
 2018-03-20 22:05:09 +05:30
Torsten Ruger
dba08ba8ce small code climate inspired clean 2018-03-20 13:48:17 +05:30
Torsten Ruger
2c6ea7ea46 finish truth check (green again) 
some (basic) if tests
 2018-03-20 13:30:38 +05:30
Torsten Ruger
8bac096f74 fix while statements each 
wasn’t picking up condition
 2018-03-20 13:29:18 +05:30
Torsten Ruger
c8980595a3 start to test if 
truth check is only half done
 2018-03-19 21:20:11 +05:30
Torsten Ruger
63c1468e1e bit of code docs 2018-03-19 21:19:46 +05:30
Torsten Ruger
cff6226297 own file for check 2018-03-19 21:19:26 +05:30
Torsten Ruger
99ced4369a adding Tue False and Nil Class to Parfait 
and boot
 2018-03-19 21:18:56 +05:30
Torsten Ruger
d195ef68da move the code to load a slot_definition to a register 
so we don’t have to copy it.
 2018-03-19 20:54:32 +05:30
Torsten Ruger
7953ef3e39 fix slot_load for higher order left arguments 
needed for getting args or frame of the target, for assigns
fixed ripples in tests
 2018-03-19 15:47:40 +05:30
Torsten Ruger
c0a7f1d284 fix insertion and add assign send 
must implement send conversion before this makes sense
 2018-03-19 13:19:42 +05:30
Torsten Ruger
66a160d8ab fix code insertion in method 2018-03-19 13:05:08 +05:30
Torsten Ruger
46ed4285a2 filing at dependencies 2018-03-18 22:36:36 +05:30
Torsten Ruger
af94d40cab passing frame (locals) into method creation 
so typed_method have correct frame information and
can resolve slots correctly (next step)
 2018-03-18 22:09:27 +05:30
Torsten Ruger
0813312ddc using compiler_for to create all building compilers 
unify api, create defaults and especially pass the right types into the
typed method creation
 2018-03-18 22:08:35 +05:30
Torsten Ruger
e7b878a353 mostly finish index resolve in slot_definition 
alas, it reveals error, types may not be set correctly
 2018-03-18 10:51:46 +05:30
Torsten Ruger
be79388cc5 remove dead code 2018-03-18 10:50:37 +05:30
Torsten Ruger
c5ec532616 use common list for risc instruction 
strange that that was not done before as the code was clearly copied
when extracting it

Fix bug for insertion
 2018-03-18 10:36:01 +05:30
Torsten Ruger
9c052c78a7 fix most of slot_load to_risc 
higher orders not working yet
 2018-03-17 21:32:09 +05:30
Torsten Ruger
cddc25a595 fixing tests for shifting constants into slots 2018-03-17 21:15:38 +05:30
Torsten Ruger
3fecdf54a5 always return slot definitions 
fixing sends defs
 2018-03-17 20:57:35 +05:30
Torsten Ruger
642f16b73a adding cache entry to parfait 2018-03-17 19:03:39 +05:30
Torsten Ruger
16c8fcbf66 first local assignment risc test 
comes with casualties
slot_load needs more work
 2018-03-17 11:13:44 +05:30
Torsten Ruger
ba3ec9b1a2 everything but dynamic dispatch 2018-03-16 19:39:35 +05:30
Torsten Ruger
d01bdf5dc5 return works 2018-03-16 19:26:27 +05:30
Torsten Ruger
259b248588 ifs working 2018-03-16 19:05:22 +05:30
Torsten Ruger
da0e1cdc5f simple sends and all whiles working 2018-03-16 18:41:17 +05:30
Torsten Ruger
35a0952943 first while test working 
fixed logic error in test framework
 2018-03-16 12:33:11 +05:30
Torsten Ruger
ea882f403a pass parfait method to to_mom 
previously it was the toll incarnation, and that is almost the same
But for the type of self. This s by definition only known in the
parfait method
And we need it off course for type checking/dispatch
 2018-03-16 11:03:29 +05:30
Torsten Ruger
3909bdcc7d method tests working again 2018-03-16 10:32:11 +05:30
Torsten Ruger
1def69c783 simple send test works again 2018-03-15 21:54:03 +05:30
Torsten Ruger
ad4690d719 move common statements into its only use in vool 2018-03-15 20:40:21 +05:30
Torsten Ruger
79bf416e58 collapsed slot classes into one 
different slot operation have different right sides
mom assignment tests work again
157 others don’t
 2018-03-15 20:33:38 +05:30
Torsten Ruger
3247c2036c moving from collect to each 
when iterating over tree.
Much cleaner, less hokuspukus methods that are noops

Mom is coming back out, but not linked yet
 2018-03-15 17:22:56 +05:30
Torsten Ruger
3702411043 first propper hoisting test 
had to change course, normalising and object creation is not possible
in one go
have to now generate random tmp vars  that will have to be picked up
later (sorted by tmp_ prefix?)
 2018-03-15 12:46:56 +05:30
Torsten Ruger
9ddcb3224c rename 2018-03-15 11:32:32 +05:30
Torsten Ruger
78ef1368de introducing expressions and constants 
not everything statement anymore (as in ruby)
basic statement tests working, rest havoc
 2018-03-15 11:24:14 +05:30
Torsten Ruger
163cad456f random tries 2018-03-15 10:46:17 +05:30
Torsten Ruger
0a9997f549 final rename remnant, green again 2018-03-14 20:29:51 +05:30
Torsten Ruger
03a4e04f7e rename self to receiver 
just because it is a keyword and can’t be used
 2018-03-14 20:26:13 +05:30
Torsten Ruger
2533842204 add traceable dummies 2018-03-14 20:25:21 +05:30
Torsten Ruger
559a797100 rename locals to frame 2018-03-14 20:24:47 +05:30
Torsten Ruger
7db329fa6b actually adding risc instructions 
fix test harness
1 working test (yeh)
 2018-03-14 17:41:09 +05:30
Torsten Ruger
79b4b07ac4 style 2018-03-14 17:39:49 +05:30