Torsten Ruger
500851d246
start on new binary creation process
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now writing into BinaryCode instead of stream
also in the risc layer, not arm, for reusability
2018-03-27 20:47:41 +03:00
Torsten Ruger
4069397fca
don't collect labels anymore
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don’t need, use binary code as the methods jump point
2018-03-27 19:06:16 +03:00
Torsten Ruger
4253d7a6b9
move assembly from assembler to machine
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id now called position
2018-03-27 18:47:39 +03:00
Torsten Ruger
4cc1d8455e
fix util namespace
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and instruction move ripples
2018-03-26 20:05:30 +03:00
Torsten Ruger
730197fbed
organise tests to where they belong
2018-03-26 19:43:03 +03:00
Torsten Ruger
3fcb4b74c7
fix binary code set_char bug
2018-03-26 19:41:30 +03:00
Torsten Ruger
a9d5e144ca
get/set word for binary code
2018-03-26 18:14:52 +03:00
Torsten Ruger
b24b65520d
remove all that label stuff
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left over after rewrite from blocks to linked list
2018-03-26 14:54:41 +03:00
Torsten Ruger
1e21177b35
just keep binary code payload at 13 for now
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there is an extra in there at the last of the last, but ok
2018-03-26 14:37:55 +03:00
Torsten Ruger
60617ca632
some binary code tests
2018-03-26 14:04:13 +03:00
Torsten Ruger
633e99466d
start to debug
2018-03-26 13:43:26 +03:00
Torsten Ruger
865a116f47
small assembler fix
2018-03-25 20:02:51 +03:00
Torsten Ruger
279fdcc1e2
really translate risc - cpu/arm
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also labels.
Actual translation/assembly is much cleaner
2018-03-25 19:38:59 +03:00
Torsten Ruger
eb7713a9f3
remove method_compiler init method
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as init is really just adding a label it is done in the method
(thus mixing the levels, “polluting” parfait with risc, but there must
be change coming that way anyway)
2018-03-25 19:37:51 +03:00
Torsten Ruger
3bd23cee28
also separate risc and cpu inits for the machine
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interpreter works on risc, but assembler off cpu
2018-03-25 19:36:00 +03:00
Torsten Ruger
3090ccffea
keep risc and cpu instructions separate in method
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that overwriting was a bit of thorn
2018-03-25 19:33:50 +03:00
Torsten Ruger
a50368c3aa
assembler will need redoing somewhat
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with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
Torsten Ruger
de7e02b0b8
remove IsSame branch from risc
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mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
Torsten Ruger
a407601f5c
fix tests from NotSame removal
2018-03-24 18:33:19 +02:00
Torsten Ruger
ad3e73d931
start on dynamic call test
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fix cache entry being not loaded
test incomplete because of missing resolve_method
2018-03-24 17:55:01 +02:00
Torsten Ruger
3ceb2c2f69
fix div10 return sequence
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did not return at all before
2018-03-24 16:51:26 +02:00
Torsten Ruger
267237b776
fix init method message setup
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was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
Torsten Ruger
65d3d5f1c9
fix tests from interpreter load change
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loading values, not Constants
2018-03-24 12:24:53 +02:00
Torsten Ruger
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
Torsten Ruger
30d2cd3af7
fix test ripples from changing return sequence
2018-03-23 20:04:29 +02:00
Torsten Ruger
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
Torsten Ruger
b4a18bc59b
mostly brackets and formatting
2018-03-23 18:55:23 +02:00
Torsten Ruger
c51e593335
test return in interpreter
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passes but does not return. dodgy
2018-03-23 11:36:20 +02:00
Torsten Ruger
f46c4d148e
more return testing
2018-03-23 11:21:41 +02:00
Torsten Ruger
55832315eb
more fix for multilevel constant load
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was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
Torsten Ruger
34903829ca
fix interpreter test harness and start testing
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interpreter on debug for now
2018-03-22 18:54:40 +02:00
Torsten Ruger
02c12996b3
return test for risc
2018-03-22 02:38:41 +05:30
Torsten Ruger
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
Torsten Ruger
01151b4ba7
make continue labels unique
2018-03-21 22:05:51 +05:30
Torsten Ruger
e0dd4e0ad7
test dynamic call
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made cache labels unique
2018-03-21 21:58:43 +05:30
Torsten Ruger
f424e58715
finish the simple call
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moving jump address
2018-03-21 19:29:00 +05:30
Torsten Ruger
49880267bb
start to test call
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as per tdd noticing logic errors, have to swap message out
2018-03-21 19:20:51 +05:30
Torsten Ruger
a9196e9cd6
implement simple_calls to_risc
2018-03-21 18:54:42 +05:30
Torsten Ruger
71c59e5bc0
remove calls from tests that don't test call
2018-03-21 16:11:57 +05:30
Torsten Ruger
fcbdba4804
simplify method entry exit codes
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Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
Torsten Ruger
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
Torsten Ruger
fa797f722d
to_risc for NotSameCheck
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which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
Torsten Ruger
12c71fa394
first go at message setups translation to risc
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simplest possible implementation, ie the method and next_messages are
loaded many times.
But the layer design shines, it’s easy to understand
2018-03-21 12:20:55 +05:30
Torsten Ruger
d9ce295b89
fix all tests from removing the receiver load
2018-03-20 23:31:42 +05:30
Torsten Ruger
77084dc894
fix unconditional jump
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and affected tests
2018-03-20 22:05:09 +05:30
Torsten Ruger
c12830ee6d
simple while risc conversion test
2018-03-20 16:32:07 +05:30
Torsten Ruger
2c6ea7ea46
finish truth check (green again)
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some (basic) if tests
2018-03-20 13:30:38 +05:30
Torsten Ruger
8bac096f74
fix while statements each
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wasn’t picking up condition
2018-03-20 13:29:18 +05:30
Torsten Ruger
c8980595a3
start to test if
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truth check is only half done
2018-03-19 21:20:11 +05:30
Torsten Ruger
81f4524c7a
move assignment test into own dir
2018-03-19 16:28:53 +05:30
