Torsten Ruger
33ffcf1d88
move resolve_method code from word to mom
...
rather make resolve an instruction.
Since it was coded in risc anyway, we not only save the setup and call
But also makes the mom instruction flow clearer
The method really came from not wanting to code it in risc, but with
the Builder, that is now surprisingly painless
2018-04-08 18:55:17 +03:00
Torsten Ruger
9867234c38
move most code from method_compiler to builder
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rather use builder in two ways, than sometimes compiler and sometimes
builder
Also makes it possible to reuse builtin code in mom’s to_risc, as both
use builder. The builtin code by directly adding to compiler, the mom
code not.
2018-04-08 18:51:20 +03:00
Torsten Ruger
6958fc31ab
rework resolve_method, using builder
2018-04-07 23:07:44 +03:00
Torsten Ruger
26cf911a5c
change build names a little and document
2018-04-07 22:35:40 +03:00
Torsten Ruger
db55ec3fd6
slightly changing built return logic
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very tempted to add immediately, but bigger change
2018-04-07 00:35:54 +03:00
Torsten Ruger
dd0d162ebf
fix the init also, was using first message twice
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not advancing after first load
2018-04-07 00:14:02 +03:00
Torsten Ruger
eea92399ee
concludes static message setup
2018-04-06 23:11:08 +03:00
Torsten Ruger
1ddbde1191
return single message for "message" ie r0
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other names, like next_message allocate a new register
2018-04-06 22:54:54 +03:00
Torsten Ruger
22409c93ee
remove >>, consistent use of <<
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makes code easier to read, like assignments
does remind of Passengers
2018-04-06 22:40:58 +03:00
Torsten Ruger
c042dd9faa
allow reverse syntax for >> (ie <<)
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slot >> reg makes sense, being a slot_to_reg
but . . .
consistently use of << (as meaning assignment , =) also makes sense
allow both and let time tell which makes more sense
2018-04-06 21:05:26 +03:00
Torsten Ruger
41d573d571
wrought one more instruction for message setup
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now with dsl ready, should be faster
2018-04-06 20:58:58 +03:00
Torsten Ruger
cae5e323ec
add reg to slot
2018-04-06 20:21:14 +03:00
Torsten Ruger
c233bd82d6
implement [] for RiscValue for the dsl
2018-04-06 16:08:35 +03:00
Torsten Ruger
e396807ee5
start work on dsl
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so i can read my own code
2018-04-06 14:21:38 +03:00
Torsten Ruger
d52e14d201
continue to rewrite message_setup
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message come from space already.
next types
2018-04-05 20:37:03 +03:00
Torsten Ruger
f09086e524
unite the two resolve_to_index functions
2018-04-05 20:10:00 +03:00
Torsten Ruger
f4ce6d6253
starting to redo message_setup
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apart from previous commits bug, it also needs to deal with
dynamic/static correctly
and while at it will do the getting from space
2018-04-05 12:24:49 +03:00
Torsten Ruger
ee0a1ca823
renaming methods args and frame
...
to arguments_type and frame_type, because that is what they are
In honour of setup bug, where the types of those types were loaded,
instead of just them types
2018-04-05 12:22:14 +03:00
Torsten Ruger
c51fc67ba5
make interpreter tests less brittle
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by factoring __init code away
just counting main
2018-04-04 20:05:09 +03:00
Torsten Ruger
65d57c8c7c
removing unconditional
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just Branch is fine
2018-04-02 19:30:34 +03:00
Torsten Ruger
a2173645b3
remove the :int shorthand
2018-03-31 19:17:55 +03:00
Torsten Ruger
cb9f6973d9
fix true false and nil constant
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going from mom to parfait
basics in place, more ripples to fix
2018-03-31 13:47:02 +03:00
Torsten Ruger
9e9b5c7f37
move to parfait integers in risc layer
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loading constants means loading parfait objects
objects have to me collected in machine
integer ok, string/true/false/nil next
2018-03-31 13:25:59 +03:00
Torsten Ruger
4cc1d8455e
fix util namespace
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and instruction move ripples
2018-03-26 20:05:30 +03:00
Torsten Ruger
bc4d4b428a
change boot to new hash syntax
2018-03-25 13:27:15 +03:00
Torsten Ruger
de7e02b0b8
remove IsSame branch from risc
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mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
Torsten Ruger
ad3e73d931
start on dynamic call test
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fix cache entry being not loaded
test incomplete because of missing resolve_method
2018-03-24 17:55:01 +02:00
Torsten Ruger
6a538624c5
remove NotSame from risc
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instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
Torsten Ruger
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
Torsten Ruger
6721153456
fix return sequence
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logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
2018-03-23 18:58:42 +02:00
Torsten Ruger
a306c464b7
start using tmp registers at 1
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which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
Torsten Ruger
55832315eb
more fix for multilevel constant load
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was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
Torsten Ruger
e505856af7
fix multi level right slot load
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was done for left, but forgotten for right
2018-03-22 18:54:07 +02:00
Torsten Ruger
6e901e1718
allow setting the source for slot loads
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so we can track more exactly which instruction created the risc
2018-03-22 18:45:03 +02:00
Torsten Ruger
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
Torsten Ruger
01151b4ba7
make continue labels unique
2018-03-21 22:05:51 +05:30
Torsten Ruger
f424e58715
finish the simple call
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moving jump address
2018-03-21 19:29:00 +05:30
Torsten Ruger
49880267bb
start to test call
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as per tdd noticing logic errors, have to swap message out
2018-03-21 19:20:51 +05:30
Torsten Ruger
b5ef929c9c
add method to risc function call
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just so we still know at compile time
2018-03-21 19:05:53 +05:30
Torsten Ruger
a9196e9cd6
implement simple_calls to_risc
2018-03-21 18:54:42 +05:30
Torsten Ruger
61a801b00c
Return to_risc
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remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
Torsten Ruger
fa797f722d
to_risc for NotSameCheck
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which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
Torsten Ruger
12c71fa394
first go at message setups translation to risc
...
simplest possible implementation, ie the method and next_messages are
loaded many times.
But the layer design shines, it’s easy to understand
2018-03-21 12:20:55 +05:30
Torsten Ruger
b99fdc3425
rename jump label
2018-03-21 11:52:53 +05:30
Torsten Ruger
d98e55907e
first go at translating DynamicCall to risc
2018-03-21 11:51:10 +05:30
Torsten Ruger
48485477c2
implement one more depth for slot_load
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soon time to make some loop
fix offset with array / object layout difference
2018-03-20 23:31:20 +05:30
Torsten Ruger
8dc0950980
implement ArgumentTransfer
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also unite with the receiver which was handled incorrectly
(left as a Vool constant)
2018-03-20 22:31:39 +05:30
Torsten Ruger
77084dc894
fix unconditional jump
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and affected tests
2018-03-20 22:05:09 +05:30
Torsten Ruger
dba08ba8ce
small code climate inspired clean
2018-03-20 13:48:17 +05:30
Torsten Ruger
2c6ea7ea46
finish truth check (green again)
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some (basic) if tests
2018-03-20 13:30:38 +05:30
Torsten Ruger
63c1468e1e
bit of code docs
2018-03-19 21:19:46 +05:30
Torsten Ruger
cff6226297
own file for check
2018-03-19 21:19:26 +05:30
Torsten Ruger
99ced4369a
adding Tue False and Nil Class to Parfait
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and boot
2018-03-19 21:18:56 +05:30
Torsten Ruger
d195ef68da
move the code to load a slot_definition to a register
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so we don’t have to copy it.
2018-03-19 20:54:32 +05:30
Torsten Ruger
7953ef3e39
fix slot_load for higher order left arguments
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needed for getting args or frame of the target, for assigns
fixed ripples in tests
2018-03-19 15:47:40 +05:30
Torsten Ruger
e7b878a353
mostly finish index resolve in slot_definition
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alas, it reveals error, types may not be set correctly
2018-03-18 10:51:46 +05:30
Torsten Ruger
be79388cc5
remove dead code
2018-03-18 10:50:37 +05:30
Torsten Ruger
9c052c78a7
fix most of slot_load to_risc
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higher orders not working yet
2018-03-17 21:32:09 +05:30
Torsten Ruger
642f16b73a
adding cache entry to parfait
2018-03-17 19:03:39 +05:30
Torsten Ruger
16c8fcbf66
first local assignment risc test
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comes with casualties
slot_load needs more work
2018-03-17 11:13:44 +05:30
Torsten Ruger
35a0952943
first while test working
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fixed logic error in test framework
2018-03-16 12:33:11 +05:30
Torsten Ruger
79bf416e58
collapsed slot classes into one
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different slot operation have different right sides
mom assignment tests work again
157 others don’t
2018-03-15 20:33:38 +05:30
Torsten Ruger
78ef1368de
introducing expressions and constants
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not everything statement anymore (as in ruby)
basic statement tests working, rest havoc
2018-03-15 11:24:14 +05:30
Torsten Ruger
163cad456f
random tries
2018-03-15 10:46:17 +05:30
Torsten Ruger
03a4e04f7e
rename self to receiver
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just because it is a keyword and can’t be used
2018-03-14 20:26:13 +05:30
Torsten Ruger
2533842204
add traceable dummies
2018-03-14 20:25:21 +05:30
Torsten Ruger
83d957377e
more precise
2018-03-14 17:37:27 +05:30
Torsten Ruger
b854c075b2
move each slot instruction into own file
2018-03-14 17:36:55 +05:30
Torsten Ruger
a3890afc20
clean up requires a bit
2018-03-13 16:57:24 +05:30
Torsten Ruger
20a88f9ac8
sorting mom instructions and statements into separate dirs
2018-03-13 16:51:33 +05:30
Torsten Ruger
96800fd8fd
starting to_risc descent
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just fleshing it for now
2018-03-13 16:16:06 +05:30
Torsten Ruger
b297650b78
adds a mom version of basic values
2018-03-13 12:30:51 +05:30
Torsten Ruger
c806106917
simple test for dynamic call
2018-03-12 18:13:26 +05:30
Torsten Ruger
e6e8522b4e
fix order of pops
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slightly embarrassingly was popping (from the end)
rather than shifting (from the start)
2018-03-12 18:13:07 +05:30
Torsten Ruger
e0f6ba7bcf
simple if test without else
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unveils many a bug that is now fixed
2018-03-12 17:56:44 +05:30
Torsten Ruger
f7aac1d1a4
polish docs
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and a bit of code style
2018-03-11 16:11:15 +05:30
Torsten Ruger
d6a2ea4cfc
fix dynamic resolve
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patch more like, real resolve method will have to be written
and put in there
2018-03-10 19:01:38 +05:30
Torsten Ruger
3a365c779a
setup to resolve method dynamically
2018-03-10 18:47:36 +05:30
Torsten Ruger
dae17e0c18
always slot definitions in slot loads
2018-03-10 18:04:04 +05:30
Torsten Ruger
2739747453
a start on dynamic dispatch (wip)
2017-09-14 16:07:02 +03:00
Torsten Ruger
afbcbca4da
extracting some of the calling into own instructions
2017-09-11 14:22:33 +03:00
Torsten Ruger
66901eeb5b
fix use of slot_constant vs slot_move
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wip
2017-09-10 12:57:25 +03:00
Torsten Ruger
d86282b007
flattening of moms while
2017-09-08 13:22:20 +03:00
Torsten Ruger
0f83b89805
correct flattening for moms if
2017-09-08 13:12:24 +03:00
Torsten Ruger
985dc9904d
copied list code from risc instructions
2017-09-08 13:10:22 +03:00
Torsten Ruger
80c3430536
replace arrays with Statements class
2017-09-06 12:51:24 +03:00
Torsten Ruger
9a1e4a6f27
own statements class for mom
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so we don’t have to deal with arrays (as a special case)
and use method sending as is good oo
2017-09-06 12:33:46 +03:00
Torsten Ruger
0e51492430
introduce statement class for mom
2017-09-06 12:11:30 +03:00
Torsten Ruger
0e98179888
fold the mini check file
2017-09-06 12:08:44 +03:00
Torsten Ruger
af85cb7c67
adds mom while
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much like the if, difference will show later in the jump arrangement
2017-09-05 12:04:52 +03:00
Torsten Ruger
1a219a7c89
introduce slot_definition and use it
2017-09-04 21:31:49 +03:00
Torsten Ruger
dab4e74659
Reworking if statement
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Using 2 phase approach
Flattening tbd
2017-09-04 21:00:08 +03:00
Torsten Ruger
db1549e0ee
Clarifying mom
2017-09-04 20:58:57 +03:00
Torsten Ruger
b6fa8261e6
first stab at moms if
2017-08-30 17:21:13 +03:00
Torsten Ruger
670ebd06cc
remove traces of salama
2017-08-29 18:38:51 +03:00
Torsten Ruger
e40346b246
one more send mom test
2017-08-29 18:28:25 +03:00
Torsten Ruger
0d43987005
start to compile send
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still very hacked version of simple call, but a start
2017-04-15 20:58:39 +03:00
Torsten Ruger
265b25d5f4
introduce return_sequence instruction to mom
2017-04-14 21:01:50 +03:00
Torsten Ruger
21e426be71
finishes local assignments to_mom
2017-04-12 14:45:02 +03:00
Torsten Ruger
9c499c7a19
actually start doing something in to_mom
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though still dummy
2017-04-12 11:53:02 +03:00