1e21177b35
just keep binary code payload at 13 for now
...
there is an extra in there at the last of the last, but ok
2018-03-26 14:37:55 +03:00
231025389a
little cleanup
...
code climate inspired
2018-03-26 14:15:48 +03:00
60617ca632
some binary code tests
2018-03-26 14:04:13 +03:00
633e99466d
start to debug
2018-03-26 13:43:26 +03:00
865a116f47
small assembler fix
2018-03-25 20:02:51 +03:00
279fdcc1e2
really translate risc - cpu/arm
...
also labels.
Actual translation/assembly is much cleaner
2018-03-25 19:38:59 +03:00
eb7713a9f3
remove method_compiler init method
...
as init is really just adding a label it is done in the method
(thus mixing the levels, “polluting” parfait with risc, but there must
be change coming that way anyway)
2018-03-25 19:37:51 +03:00
3bd23cee28
also separate risc and cpu inits for the machine
...
interpreter works on risc, but assembler off cpu
2018-03-25 19:36:00 +03:00
3090ccffea
keep risc and cpu instructions separate in method
...
that overwriting was a bit of thorn
2018-03-25 19:33:50 +03:00
a50368c3aa
assembler will need redoing somewhat
...
with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
82ab8ac4d3
add data objects
...
marker class (may change) to be able to check access
2018-03-25 18:22:02 +03:00
bc4d4b428a
change boot to new hash syntax
2018-03-25 13:27:15 +03:00
de7e02b0b8
remove IsSame branch from risc
...
mixing up levels, IsSame is Mom
at risc this is a minus and Zero check
fix all tests
2018-03-24 18:54:36 +02:00
a407601f5c
fix tests from NotSame removal
2018-03-24 18:33:19 +02:00
8cee2db1d1
return just gets the register (no more offset)
...
use mov instead
2018-03-24 18:32:53 +02:00
ad3e73d931
start on dynamic call test
...
fix cache entry being not loaded
test incomplete because of missing resolve_method
2018-03-24 17:55:01 +02:00
6a538624c5
remove NotSame from risc
...
instead use a - b and then isZero
2018-03-24 17:54:15 +02:00
793fa313a5
change operators to symbols
2018-03-24 17:53:27 +02:00
3ceb2c2f69
fix div10 return sequence
...
did not return at all before
2018-03-24 16:51:26 +02:00
267237b776
fix init method message setup
...
was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
65d3d5f1c9
fix tests from interpreter load change
...
loading values, not Constants
2018-03-24 12:24:53 +02:00
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
30d2cd3af7
fix test ripples from changing return sequence
2018-03-23 20:04:29 +02:00
0f183b3a74
fix value return and test
...
slot load was wrong way around
2018-03-23 20:02:17 +02:00
6721153456
fix return sequence
...
logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
2018-03-23 18:58:42 +02:00
a306c464b7
start using tmp registers at 1
...
which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
472b1a638a
add register logging and fix function return
...
return semantics used to be different, now only register is given
2018-03-23 18:56:38 +02:00
b4a18bc59b
mostly brackets and formatting
2018-03-23 18:55:23 +02:00
c51e593335
test return in interpreter
...
passes but does not return. dodgy
2018-03-23 11:36:20 +02:00
f46c4d148e
more return testing
2018-03-23 11:21:41 +02:00
55832315eb
more fix for multilevel constant load
...
was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
34903829ca
fix interpreter test harness and start testing
...
interpreter on debug for now
2018-03-22 18:54:40 +02:00
e505856af7
fix multi level right slot load
...
was done for left, but forgotten for right
2018-03-22 18:54:07 +02:00
6e901e1718
allow setting the source for slot loads
...
so we can track more exactly which instruction created the risc
2018-03-22 18:45:03 +02:00
9932d0bf33
add source to the to_s
2018-03-22 18:38:19 +02:00
19afc376f4
fix local name being string (not symbol)
2018-03-22 21:08:13 +05:30
769fd71a3d
fix redefining typed methods
...
as happens for predefined Space.main
2018-03-22 21:06:22 +05:30
02c12996b3
return test for risc
2018-03-22 02:38:41 +05:30
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
01151b4ba7
make continue labels unique
2018-03-21 22:05:51 +05:30
e0dd4e0ad7
test dynamic call
...
made cache labels unique
2018-03-21 21:58:43 +05:30
f424e58715
finish the simple call
...
moving jump address
2018-03-21 19:29:00 +05:30
49880267bb
start to test call
...
as per tdd noticing logic errors, have to swap message out
2018-03-21 19:20:51 +05:30
b5ef929c9c
add method to risc function call
...
just so we still know at compile time
2018-03-21 19:05:53 +05:30
a9196e9cd6
implement simple_calls to_risc
2018-03-21 18:54:42 +05:30
71c59e5bc0
remove calls from tests that don't test call
2018-03-21 16:11:57 +05:30
fcbdba4804
simplify method entry exit codes
...
Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
61a801b00c
Return to_risc
...
remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
fa797f722d
to_risc for NotSameCheck
...
which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
