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4888b3b6db
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Starting to rework slot instructions that create risc
have to go through all and all macros and all thems tests. What did the wise man say: one step at a time
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2020-03-22 14:31:43 +02:00 |
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4643be0ae6
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codong RegisterSlot with reg and slot
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2020-03-22 14:31:43 +02:00 |
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d22da1ab97
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SA for slot_to_reg
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2020-03-22 14:31:43 +02:00 |
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Torsten Ruger
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3bc85805a4
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must pass registers to slot_to_reg and reg_to_slot
as they are typed, those functions don't resolve on Risc, but the register type
miscother changes from previous commits
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2018-07-15 16:30:50 +03:00 |
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Torsten Ruger
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f09086e524
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unite the two resolve_to_index functions
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2018-04-05 20:10:00 +03:00 |
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Torsten Ruger
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b4489b1093
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rename RiscTransfer to Transfer
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2018-03-21 15:48:04 +05:30 |
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Torsten Ruger
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aa79e41d1c
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rename register to risc
seems to fit the layer much better as we really have a very reduced
instruction set
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2017-01-19 09:02:29 +02:00 |
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