Torsten Ruger
6721153456
fix return sequence
...
logic error of swapping messages too soon
simplify by folding message unto itself
thus only need one extra register for the address
2018-03-23 18:58:42 +02:00
Torsten Ruger
a306c464b7
start using tmp registers at 1
...
which used to be reserved for the next message
2018-03-23 18:57:16 +02:00
Torsten Ruger
55832315eb
more fix for multilevel constant load
...
was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
Torsten Ruger
e505856af7
fix multi level right slot load
...
was done for left, but forgotten for right
2018-03-22 18:54:07 +02:00
Torsten Ruger
6e901e1718
allow setting the source for slot loads
...
so we can track more exactly which instruction created the risc
2018-03-22 18:45:03 +02:00
Torsten Ruger
ca3bf6acfa
fix constants being passed down
2018-03-22 02:38:06 +05:30
Torsten Ruger
01151b4ba7
make continue labels unique
2018-03-21 22:05:51 +05:30
Torsten Ruger
f424e58715
finish the simple call
...
moving jump address
2018-03-21 19:29:00 +05:30
Torsten Ruger
49880267bb
start to test call
...
as per tdd noticing logic errors, have to swap message out
2018-03-21 19:20:51 +05:30
Torsten Ruger
b5ef929c9c
add method to risc function call
...
just so we still know at compile time
2018-03-21 19:05:53 +05:30
Torsten Ruger
a9196e9cd6
implement simple_calls to_risc
2018-03-21 18:54:42 +05:30
Torsten Ruger
61a801b00c
Return to_risc
...
remove the index from FunctionReturn, just jump to the register address
2018-03-21 15:48:50 +05:30
Torsten Ruger
fa797f722d
to_risc for NotSameCheck
...
which is only used in call cache checking
some fixing, needed to add a abel for the cache check jump
2018-03-21 12:38:28 +05:30
Torsten Ruger
12c71fa394
first go at message setups translation to risc
...
simplest possible implementation, ie the method and next_messages are
loaded many times.
But the layer design shines, it’s easy to understand
2018-03-21 12:20:55 +05:30
Torsten Ruger
b99fdc3425
rename jump label
2018-03-21 11:52:53 +05:30
Torsten Ruger
d98e55907e
first go at translating DynamicCall to risc
2018-03-21 11:51:10 +05:30
Torsten Ruger
48485477c2
implement one more depth for slot_load
...
soon time to make some loop
fix offset with array / object layout difference
2018-03-20 23:31:20 +05:30
Torsten Ruger
8dc0950980
implement ArgumentTransfer
...
also unite with the receiver which was handled incorrectly
(left as a Vool constant)
2018-03-20 22:31:39 +05:30
Torsten Ruger
77084dc894
fix unconditional jump
...
and affected tests
2018-03-20 22:05:09 +05:30
Torsten Ruger
dba08ba8ce
small code climate inspired clean
2018-03-20 13:48:17 +05:30
Torsten Ruger
2c6ea7ea46
finish truth check (green again)
...
some (basic) if tests
2018-03-20 13:30:38 +05:30
Torsten Ruger
63c1468e1e
bit of code docs
2018-03-19 21:19:46 +05:30
Torsten Ruger
cff6226297
own file for check
2018-03-19 21:19:26 +05:30
Torsten Ruger
99ced4369a
adding Tue False and Nil Class to Parfait
...
and boot
2018-03-19 21:18:56 +05:30
Torsten Ruger
d195ef68da
move the code to load a slot_definition to a register
...
so we don’t have to copy it.
2018-03-19 20:54:32 +05:30
Torsten Ruger
7953ef3e39
fix slot_load for higher order left arguments
...
needed for getting args or frame of the target, for assigns
fixed ripples in tests
2018-03-19 15:47:40 +05:30
Torsten Ruger
e7b878a353
mostly finish index resolve in slot_definition
...
alas, it reveals error, types may not be set correctly
2018-03-18 10:51:46 +05:30
Torsten Ruger
be79388cc5
remove dead code
2018-03-18 10:50:37 +05:30
Torsten Ruger
9c052c78a7
fix most of slot_load to_risc
...
higher orders not working yet
2018-03-17 21:32:09 +05:30
Torsten Ruger
642f16b73a
adding cache entry to parfait
2018-03-17 19:03:39 +05:30
Torsten Ruger
16c8fcbf66
first local assignment risc test
...
comes with casualties
slot_load needs more work
2018-03-17 11:13:44 +05:30
Torsten Ruger
35a0952943
first while test working
...
fixed logic error in test framework
2018-03-16 12:33:11 +05:30
Torsten Ruger
79bf416e58
collapsed slot classes into one
...
different slot operation have different right sides
mom assignment tests work again
157 others don’t
2018-03-15 20:33:38 +05:30
Torsten Ruger
78ef1368de
introducing expressions and constants
...
not everything statement anymore (as in ruby)
basic statement tests working, rest havoc
2018-03-15 11:24:14 +05:30
Torsten Ruger
163cad456f
random tries
2018-03-15 10:46:17 +05:30
Torsten Ruger
03a4e04f7e
rename self to receiver
...
just because it is a keyword and can’t be used
2018-03-14 20:26:13 +05:30
Torsten Ruger
2533842204
add traceable dummies
2018-03-14 20:25:21 +05:30
Torsten Ruger
83d957377e
more precise
2018-03-14 17:37:27 +05:30
Torsten Ruger
b854c075b2
move each slot instruction into own file
2018-03-14 17:36:55 +05:30
Torsten Ruger
a3890afc20
clean up requires a bit
2018-03-13 16:57:24 +05:30
Torsten Ruger
20a88f9ac8
sorting mom instructions and statements into separate dirs
2018-03-13 16:51:33 +05:30
Torsten Ruger
96800fd8fd
starting to_risc descent
...
just fleshing it for now
2018-03-13 16:16:06 +05:30
Torsten Ruger
b297650b78
adds a mom version of basic values
2018-03-13 12:30:51 +05:30
Torsten Ruger
c806106917
simple test for dynamic call
2018-03-12 18:13:26 +05:30
Torsten Ruger
e6e8522b4e
fix order of pops
...
slightly embarrassingly was popping (from the end)
rather than shifting (from the start)
2018-03-12 18:13:07 +05:30
Torsten Ruger
e0f6ba7bcf
simple if test without else
...
unveils many a bug that is now fixed
2018-03-12 17:56:44 +05:30
Torsten Ruger
f7aac1d1a4
polish docs
...
and a bit of code style
2018-03-11 16:11:15 +05:30
Torsten Ruger
d6a2ea4cfc
fix dynamic resolve
...
patch more like, real resolve method will have to be written
and put in there
2018-03-10 19:01:38 +05:30
Torsten Ruger
3a365c779a
setup to resolve method dynamically
2018-03-10 18:47:36 +05:30
Torsten Ruger
dae17e0c18
always slot definitions in slot loads
2018-03-10 18:04:04 +05:30
Torsten Ruger
2739747453
a start on dynamic dispatch (wip)
2017-09-14 16:07:02 +03:00
Torsten Ruger
afbcbca4da
extracting some of the calling into own instructions
2017-09-11 14:22:33 +03:00
Torsten Ruger
66901eeb5b
fix use of slot_constant vs slot_move
...
wip
2017-09-10 12:57:25 +03:00
Torsten Ruger
d86282b007
flattening of moms while
2017-09-08 13:22:20 +03:00
Torsten Ruger
0f83b89805
correct flattening for moms if
2017-09-08 13:12:24 +03:00
Torsten Ruger
985dc9904d
copied list code from risc instructions
2017-09-08 13:10:22 +03:00
Torsten Ruger
80c3430536
replace arrays with Statements class
2017-09-06 12:51:24 +03:00
Torsten Ruger
9a1e4a6f27
own statements class for mom
...
so we don’t have to deal with arrays (as a special case)
and use method sending as is good oo
2017-09-06 12:33:46 +03:00
Torsten Ruger
0e51492430
introduce statement class for mom
2017-09-06 12:11:30 +03:00
Torsten Ruger
0e98179888
fold the mini check file
2017-09-06 12:08:44 +03:00
Torsten Ruger
af85cb7c67
adds mom while
...
much like the if, difference will show later in the jump arrangement
2017-09-05 12:04:52 +03:00
Torsten Ruger
1a219a7c89
introduce slot_definition and use it
2017-09-04 21:31:49 +03:00
Torsten Ruger
dab4e74659
Reworking if statement
...
Using 2 phase approach
Flattening tbd
2017-09-04 21:00:08 +03:00
Torsten Ruger
db1549e0ee
Clarifying mom
2017-09-04 20:58:57 +03:00
Torsten Ruger
b6fa8261e6
first stab at moms if
2017-08-30 17:21:13 +03:00
Torsten Ruger
670ebd06cc
remove traces of salama
2017-08-29 18:38:51 +03:00
Torsten Ruger
e40346b246
one more send mom test
2017-08-29 18:28:25 +03:00
Torsten Ruger
0d43987005
start to compile send
...
still very hacked version of simple call, but a start
2017-04-15 20:58:39 +03:00
Torsten Ruger
265b25d5f4
introduce return_sequence instruction to mom
2017-04-14 21:01:50 +03:00
Torsten Ruger
21e426be71
finishes local assignments to_mom
2017-04-12 14:45:02 +03:00
Torsten Ruger
9c499c7a19
actually start doing something in to_mom
...
though still dummy
2017-04-12 11:53:02 +03:00
Torsten Ruger
0233e91355
basic mom directory structure and a readme
2017-04-10 11:47:18 +03:00
