Commit Graph

5 Commits

Author SHA1 Message Date
d22da1ab97 SA for slot_to_reg 2020-03-22 14:31:43 +02:00
Torsten Ruger
3bc85805a4 must pass registers to slot_to_reg and reg_to_slot
as they are typed, those functions don't resolve on Risc, but the register type
miscother changes from previous commits
2018-07-15 16:30:50 +03:00
Torsten Ruger
f09086e524 unite the two resolve_to_index functions 2018-04-05 20:10:00 +03:00
Torsten Ruger
b4489b1093 rename RiscTransfer to Transfer 2018-03-21 15:48:04 +05:30
Torsten Ruger
aa79e41d1c rename register to risc
seems to fit the layer much better as we really have a very reduced
instruction set
2017-01-19 09:02:29 +02:00