rename left to first in instruction and started on logic instruction cleanup
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@@ -6,15 +6,15 @@ module Arm
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include Arm::Constants
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include LogicHelper
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def initialize(left , attributes)
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super(left , attributes)
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def initialize(first , attributes)
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super(first , attributes)
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@attributes[:update_status_flag] = 0 if @attributes[:update_status_flag] == nil
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@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
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@attributes[:opcode] = attributes[:opcode]
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@operand = 0
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@i = 0
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@rd = @left
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@rd = @first
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@rn = :r0 # register zero = zero bit pattern
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end
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