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fix mod4

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which is just shift right by 2 after all
This commit is contained in:
Torsten Ruger 2018-04-01 15:13:12 +03:00
parent 10fa61aa9f
commit def67205f0
2 changed files with 38 additions and 37 deletions
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16
lib/risc/builtin/integer.rb
View File

@ -3,14 +3,22 @@ module Risc
module Builtin
module Integer
module ClassMethods
include AST::Sexp
include CompileHelper
def mod4 context
def mod4(context)
source = "mod4"
compiler = compiler_for(:Integer,:mod4 ,{})
me = compiler.add_known( :receiver )
compiler.reduce_int( source , me )
two = compiler.use_reg :fixnum , 2
compiler.add_load_data( source , 2 , two )
compiler.add_code Risc.op( source , :>> , me , two)
compiler.add_new_int(me , two)
compiler.add_reg_to_slot( source , two , :message , :return_value)
compiler.add_mom( Mom::ReturnSequence.new)
return compiler.method
end
def putint context
def putint(context)
compiler = compiler_for(:Integer,:putint ,{})
return compiler.method
end
@ -19,7 +27,6 @@ module Risc
source = "plus"
compiler = compiler_for(:Integer,:+ ,{other: :Integer})
me , other = compiler.self_and_int_arg(source + "1")
# reduce me and other to integers
compiler.reduce_int( source + "2", me )
compiler.reduce_int( source + "3", other )
compiler.add_code Risc.op( source + "4", :+ , me , other)
@ -31,6 +38,7 @@ module Risc
def div10( context )
s = "div_10 "
compiler = compiler_for(:Integer,:div10 ,{})
#FIX: this could load receiver once, reduce and then transfer twice
me = compiler.add_known( :receiver )
tmp = compiler.add_known( :receiver )
q = compiler.add_known( :receiver )

59
test/risc/interpreter/test_mod.rb
View File

@ -5,7 +5,7 @@ module Risc
include Ticker
def setup
@string_input = as_main "return 5.mod4"
@string_input = as_main "return 9.mod4"
super
end
@ -21,43 +21,36 @@ module Risc
RegToSlot, LoadConstant, SlotToReg, SlotToReg, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant,
FunctionCall, Label, Label, NilClass]
FunctionCall, Label, SlotToReg, SlotToReg, LoadData,
OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg,
RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn,
Transfer, Syscall, NilClass]
assert_equal Parfait::Integer , get_return.class
assert_equal 2 , get_return.value
end
def test_get
assert_equal SlotToReg , ticks(4).class
assert @interpreter.get_register( :r2 )
assert Integer , @interpreter.get_register( :r2 ).class
def test_load
lod = ticks(43)
assert_equal LoadConstant , lod.class
assert_equal 9 , lod.constant.value
end
def pest_transfer
transfer = ticks 19
assert_equal Transfer , transfer.class
assert_equal @interpreter.get_register(transfer.to) , @interpreter.get_register(transfer.from)
def test_fix # reduce self to fix
sl = ticks(54)
assert_equal SlotToReg , sl.class
assert_equal :r1 , sl.array.symbol
assert_equal 3 , sl.index
assert_equal :r1 , sl.register.symbol
assert_equal 9 , @interpreter.get_register(:r1)
end
def pest_call
ret = ticks(18)
assert_equal FunctionReturn , ret.class
object = @interpreter.get_register( ret.register )
link = object.get_internal_word( ret.index )
assert_equal Label , link.class
end
def pest_adding
done_op = ticks(12)
assert_equal OperatorInstruction , done_op.class
left = @interpreter.get_register(done_op.left)
rr = done_op.right
right = @interpreter.get_register(rr)
assert_equal Fixnum , left.class
assert_equal Fixnum , right.class
assert_equal 7 , right
assert_equal 12 , left
done_tr = ticks(1)
assert_equal RegToSlot , done_tr.class
result = @interpreter.get_register(done_op.left)
assert_equal result , 12
def test_sys
sys = ticks(82)
assert_equal Syscall , sys.class
assert_equal :exit , sys.name
end
end
end