whitespace round plusses
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@ -97,15 +97,15 @@ module Arm
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val = shift(val , 0 ) # for the test
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val |= shift(op , 0)
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val |= shift(reg_code(@result) , 12 )
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val |= shift(reg_code(rn) , 12+4) #16
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val |= shift(@is_load , 12+4 +4)
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val |= shift(w , 12+4 +4+1)
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val |= shift(byte_access , 12+4 +4+1+1)
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val |= shift(add_offset , 12+4 +4+1+1+1)
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val |= shift(@pre_post_index, 12+4 +4+1+1+1+1)#24
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val |= shift(i , 12+4 +4+1+1+1+1 +1)
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val |= shift(instuction_class,12+4 +4+1+1+1+1 +1+1)
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val |= shift(cond_bit_code , 12+4 +4+1+1+1+1 +1+1+2)
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val |= shift(reg_code(rn) , 12 + 4) #16
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val |= shift(@is_load , 12 + 4 + 4)
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val |= shift(w , 12 + 4 + 4 + 1)
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val |= shift(byte_access , 12 + 4 + 4 + 1 + 1)
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val |= shift(add_offset , 12 + 4 + 4 + 1 + 1 + 1)
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val |= shift(@pre_post_index, 12 + 4 + 4 + 1 + 1 + 1 + 1)#24
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val |= shift(i , 12 + 4 + 4 + 1 + 1 + 1 + 1 + 1)
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val |= shift(instuction_class,12 + 4 + 4 + 1 + 1 + 1 + 1 + 1 + 1)
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val |= shift(cond_bit_code , 12 + 4 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 2)
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io.write_uint32 val
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end
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