diff --git a/lib/arm/instructions/compare_instruction.rb b/lib/arm/instructions/compare_instruction.rb
index 8247bcdd..60c4c904 100644
--- a/lib/arm/instructions/compare_instruction.rb
+++ b/lib/arm/instructions/compare_instruction.rb
@@ -58,12 +58,12 @@ module Arm
       val = shift(val , 0)
       raise inspect unless reg_code(@rd)
       val |= shift(reg_code(@rd) ,            12)
-      val |= shift(reg_code(rn) ,            12+4)
-      val |= shift(@attributes[:update_status] , 12+4+4)#20
-      val |= shift(op_bit_code ,        12+4+4  +1)
-      val |= shift(immediate ,                  12+4+4  +1+4)
-      val |= shift(instuction_class ,   12+4+4  +1+4+1)
-      val |= shift(cond_bit_code ,      12+4+4  +1+4+1+2)
+      val |= shift(reg_code(rn) ,            12 + 4)
+      val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
+      val |= shift(op_bit_code ,        12 + 4 + 4  + 1)
+      val |= shift(immediate ,                  12 + 4 + 4  + 1 + 4)
+      val |= shift(instuction_class ,   12 + 4 + 4  + 1 + 4 + 1)
+      val |= shift(cond_bit_code ,      12 + 4 + 4  + 1 + 4 + 1 + 2)
       io.write_uint32 val
     end
 
@@ -92,7 +92,7 @@ module Arm
       # elsif (arg.type == 'rrx')
       #   shift_imm = 0
       # end
-      # operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
+      # operand = rm_ref | (shift_op << 4) | (shift_imm << 4 +3)
     end
     def to_s
       "#{opcode} #{@left} , #{@right} #{super}"
diff --git a/lib/arm/instructions/logic_instruction.rb b/lib/arm/instructions/logic_instruction.rb
index eef48a1b..18f98997 100644
--- a/lib/arm/instructions/logic_instruction.rb
+++ b/lib/arm/instructions/logic_instruction.rb
@@ -84,12 +84,12 @@ module Arm
       val = shift(operand , 0)
       val |= shift(op , 0) # any barrel action, is already shifted
       val |= shift(result ,            12)
-      val |= shift(left_code ,            12+4)
-      val |= shift(@attributes[:update_status] , 12+4+4)#20
-      val |= shift(op_bit_code ,        12+4+4  + 1)
-      val |= shift(immediate ,                  12+4+4  + 1+4)
-      val |= shift(instuction_class ,   12+4+4  + 1+4+1)
-      val |= shift(cond_bit_code ,      12+4+4  + 1+4+1+2)
+      val |= shift(left_code ,            12 + 4)
+      val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
+      val |= shift(op_bit_code ,        12 + 4 + 4  + 1)
+      val |= shift(immediate ,                  12 + 4 + 4  + 1 + 4)
+      val |= shift(instuction_class ,   12 + 4 + 4  + 1 + 4 + 1)
+      val |= shift(cond_bit_code ,      12 + 4 + 4  + 1 + 4 + 1 + 2)
       io.write_uint32 val
       # by now we have the extra add so assemble that
       if(@extra)
diff --git a/lib/arm/instructions/memory_instruction.rb b/lib/arm/instructions/memory_instruction.rb
index 7805da4f..5f3a7b80 100644
--- a/lib/arm/instructions/memory_instruction.rb
+++ b/lib/arm/instructions/memory_instruction.rb
@@ -97,15 +97,15 @@ module Arm
       val = shift(val , 0 ) # for the test
       val |= shift(op , 0)
       val |= shift(reg_code(@result) ,        12 )
-      val |= shift(reg_code(rn) ,        12+4) #16
-      val |= shift(@is_load ,        12+4  +4)
-      val |= shift(w ,              12+4  +4+1)
-      val |= shift(byte_access ,    12+4  +4+1+1)
-      val |= shift(add_offset ,    12+4  +4+1+1+1)
-      val |= shift(@pre_post_index, 12+4  +4+1+1+1+1)#24
-      val |= shift(i ,              12+4  +4+1+1+1+1  +1)
-      val |= shift(instuction_class,12+4  +4+1+1+1+1  +1+1)
-      val |= shift(cond_bit_code ,  12+4  +4+1+1+1+1  +1+1+2)
+      val |= shift(reg_code(rn) ,        12 + 4) #16
+      val |= shift(@is_load ,        12 + 4  + 4)
+      val |= shift(w ,              12 + 4  + 4 + 1)
+      val |= shift(byte_access ,    12 + 4  + 4 + 1 + 1)
+      val |= shift(add_offset ,    12 + 4  + 4 + 1 + 1 + 1)
+      val |= shift(@pre_post_index, 12 + 4  + 4 + 1 + 1 + 1 + 1)#24
+      val |= shift(i ,              12 + 4  + 4 + 1 + 1 + 1 + 1  + 1)
+      val |= shift(instuction_class,12 + 4  + 4 + 1 + 1 + 1 + 1  + 1 + 1)
+      val |= shift(cond_bit_code ,  12 + 4  + 4 + 1 + 1 + 1 + 1  + 1 + 1 + 2)
       io.write_uint32 val
     end
 
diff --git a/lib/arm/instructions/move_instruction.rb b/lib/arm/instructions/move_instruction.rb
index e2d98e75..96c4294c 100644
--- a/lib/arm/instructions/move_instruction.rb
+++ b/lib/arm/instructions/move_instruction.rb
@@ -88,12 +88,12 @@ module Arm
       val = shift(operand , 0)
       val |= shift(op , 0) # any barrel action, is already shifted
       val |= shift(reg_code(@to) ,            12)
-      val |= shift(reg_code(rn) ,            12+4)
-      val |= shift(@attributes[:update_status] , 12+4+4)#20
-      val |= shift(op_bit_code ,        12+4+4  + 1)
-      val |= shift(immediate ,          12+4+4  + 1+4)
-      val |= shift(instuction_class ,   12+4+4  + 1+4+1)
-      val |= shift(cond_bit_code ,      12+4+4  + 1+4+1+2)
+      val |= shift(reg_code(rn) ,            12 + 4)
+      val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
+      val |= shift(op_bit_code ,        12 + 4 + 4  + 1)
+      val |= shift(immediate ,          12 + 4 + 4  + 1 + 4)
+      val |= shift(instuction_class ,   12 + 4 + 4  + 1 + 4 + 1)
+      val |= shift(cond_bit_code ,      12 + 4 + 4  + 1 + 4 + 1 + 2)
       io.write_uint32 val
       # by now we have the extra add so assemble that
       if(@extra)
diff --git a/lib/arm/instructions/stack_instruction.rb b/lib/arm/instructions/stack_instruction.rb
index ac9942d8..33e75142 100644
--- a/lib/arm/instructions/stack_instruction.rb
+++ b/lib/arm/instructions/stack_instruction.rb
@@ -49,13 +49,13 @@ module Arm
       #assemble of old
       val = operand
       val = val | (reg_code(@rn) <<             16)
-      val = val | (is_pop <<              16+4) #20
-      val = val | (write_base <<          16+4+ 1)
-      val = val | (@attributes[:update_status] <<  16+4+ 1+1)
-      val = val | (up_down <<             16+4+ 1+1+1)
-      val = val | (pre_post_index <<      16+4+ 1+1+1+1)#24
-      val = val | (instuction_class <<    16+4+ 1+1+1+1 +2)
-      val = val | (cond <<                16+4+ 1+1+1+1 +2+2)
+      val = val | (is_pop <<              16 + 4) #20
+      val = val | (write_base <<          16 + 4 + 1)
+      val = val | (@attributes[:update_status] <<  16 + 4 + 1 + 1)
+      val = val | (up_down <<             16 + 4 + 1 + 1 + 1)
+      val = val | (pre_post_index <<      16 + 4 + 1 + 1 + 1 + 1)#24
+      val = val | (instuction_class <<    16 + 4 + 1 + 1 + 1 + 1 + 2)
+      val = val | (cond <<                16 + 4 + 1 + 1 + 1 + 1 + 2 + 2)
       io.write_uint32 val
     end