whitespace round plusses
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@ -58,12 +58,12 @@ module Arm
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val = shift(val , 0)
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raise inspect unless reg_code(@rd)
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val |= shift(reg_code(@rd) , 12)
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val |= shift(reg_code(rn) , 12+4)
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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val |= shift(op_bit_code , 12+4+4 +1)
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val |= shift(immediate , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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val |= shift(reg_code(rn) , 12 + 4)
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val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
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val |= shift(op_bit_code , 12 + 4 + 4 + 1)
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= shift(instuction_class , 12 + 4 + 4 + 1 + 4 + 1)
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val |= shift(cond_bit_code , 12 + 4 + 4 + 1 + 4 + 1 + 2)
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io.write_uint32 val
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end
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@ -92,7 +92,7 @@ module Arm
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# elsif (arg.type == 'rrx')
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# shift_imm = 0
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# end
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# operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
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# operand = rm_ref | (shift_op << 4) | (shift_imm << 4 +3)
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end
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def to_s
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"#{opcode} #{@left} , #{@right} #{super}"
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