some common instruction extration
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@ -23,6 +23,14 @@ module Arm
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val << by
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val << by
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end
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end
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def condition_code
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shift(cond_bit_code , 28 )
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end
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def instruction_code
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shift(instuction_class , 26)
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end
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def byte_length
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def byte_length
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4
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4
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end
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end
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@ -46,8 +46,8 @@ module Arm
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val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
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val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
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val |= shift(op_bit_code , 12 + 4 + 4 + 1)
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val |= shift(op_bit_code , 12 + 4 + 4 + 1)
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= shift(instuction_class , 12 + 4 + 4 + 1 + 4 + 1)
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val |= instruction_code
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val |= shift(cond_bit_code , 12 + 4 + 4 + 1 + 4 + 1 + 2)
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val |= condition_code
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io.write_uint32 val
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io.write_uint32 val
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assemble_extra
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assemble_extra
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end
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end
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@ -55,7 +55,6 @@ module Arm
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#not sure about these 2 constants. They produce the correct output for str r0 , r1
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#not sure about these 2 constants. They produce the correct output for str r0 , r1
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# but i can't help thinking that that is because they are not used in that instruction and
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# but i can't help thinking that that is because they are not used in that instruction and
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# so it doesn't matter. Will see
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# so it doesn't matter. Will see
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instuction_class = 0b01 # OPC_MEMORY_ACCESS
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if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterValue))
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if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterValue))
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val = reg_code(operand)
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val = reg_code(operand)
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@pre_post_index = 0
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@pre_post_index = 0
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@ -79,11 +78,14 @@ module Arm
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val |= shift(add_offset , 12 + 4 + 4 + 1 + 1 + 1)
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val |= shift(add_offset , 12 + 4 + 4 + 1 + 1 + 1)
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val |= shift(@pre_post_index, 12 + 4 + 4 + 1 + 1 + 1 + 1)#24
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val |= shift(@pre_post_index, 12 + 4 + 4 + 1 + 1 + 1 + 1)#24
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val |= shift(i , 12 + 4 + 4 + 1 + 1 + 1 + 1 + 1)
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val |= shift(i , 12 + 4 + 4 + 1 + 1 + 1 + 1 + 1)
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val |= shift(instuction_class,12 + 4 + 4 + 1 + 1 + 1 + 1 + 1 + 1)
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val |= instruction_code
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val |= shift(cond_bit_code , 12 + 4 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 2)
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val |= condition_code
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io.write_uint32 val
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io.write_uint32 val
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end
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end
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def instuction_class
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0b01 # OPC_MEMORY_ACCESS
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end
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def add_offset
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def add_offset
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@attributes[:add_offset] ? 0 : 1
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@attributes[:add_offset] ? 0 : 1
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end
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end
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@ -54,8 +54,8 @@ module Arm
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val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
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val |= shift(@attributes[:update_status] , 12 + 4 + 4)#20
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val |= shift(op_bit_code , 12 + 4 + 4 + 1)
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val |= shift(op_bit_code , 12 + 4 + 4 + 1)
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= shift(instuction_class , 12 + 4 + 4 + 1 + 4 + 1)
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val |= instruction_code
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val |= shift(cond_bit_code , 12 + 4 + 4 + 1 + 4 + 1 + 2)
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val |= condition_code
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io.write_uint32 val
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io.write_uint32 val
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# by now we have the extra add so assemble that
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# by now we have the extra add so assemble that
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@extra.assemble(io) if(@extra) #puts "Assemble extra at #{val.to_s(16)}"
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@extra.assemble(io) if(@extra) #puts "Assemble extra at #{val.to_s(16)}"
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@ -30,7 +30,7 @@ module Arm
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val = val | (@attributes[:update_status] << 16 + 4 + 1 + 1)
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val = val | (@attributes[:update_status] << 16 + 4 + 1 + 1)
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val = val | (up_down << 16 + 4 + 1 + 1 + 1)
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val = val | (up_down << 16 + 4 + 1 + 1 + 1)
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val = val | (pre_post_index << 16 + 4 + 1 + 1 + 1 + 1)#24
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val = val | (pre_post_index << 16 + 4 + 1 + 1 + 1 + 1)#24
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val = val | (instuction_class << 16 + 4 + 1 + 1 + 1 + 1 + 2)
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val = val | instruction_code
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val = val | (cond << 16 + 4 + 1 + 1 + 1 + 1 + 2 + 2)
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val = val | (cond << 16 + 4 + 1 + 1 + 1 + 1 + 2 + 2)
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io.write_uint32 val
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io.write_uint32 val
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end
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end
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