rename RiscTransfer to Transfer

This commit is contained in:
Torsten Ruger 2018-03-21 15:48:04 +05:30
parent fa797f722d
commit b4489b1093
15 changed files with 38 additions and 38 deletions

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@ -31,7 +31,7 @@ module Arm
ArmMachine.str( :lr , code.register , arm_index(code) )
end
def translate_RiscTransfer( code )
def translate_Transfer( code )
# Risc machine convention is from => to
# But arm has the receiver/result as the first
ArmMachine.mov( code.to , code.from)

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@ -7,7 +7,7 @@ module Risc
# This is because that is what cpu's can do. In programming terms this would be accessing
# an element in an array, in the case of RegToSlot setting the register in the array.
# btw: to move data between registers, use RiscTransfer
# btw: to move data between registers, use Transfer
class RegToSlot < Setter

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@ -7,7 +7,7 @@ module Risc
# This is because that is what cpu's can do. In programming terms this would be accessing
# an element in an array, in the case of SlotToReg setting the value in the array.
# btw: to move data between registers, use RiscTransfer
# btw: to move data between registers, use Transfer
class SlotToReg < Getter

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@ -1,6 +1,6 @@
module Risc
# transfer the constents of one register to another.
# Transfer the constents of one register to another.
# possibly called move in some cpus
# There are other instructions to move data from / to memory, namely SlotToReg and RegToSlot
@ -10,13 +10,13 @@ module Risc
# Also it is used for moving temorary data
#
class RiscTransfer < Instruction
class Transfer < Instruction
# initialize with from and to registers.
# First argument from
# second argument to
#
# Note: this may be reversed from some assembler notations (also arm)
def initialize source , from , to
def initialize( source , from , to )
super(source)
@from = from
@to = to
@ -26,10 +26,10 @@ module Risc
attr_reader :from, :to
def to_s
"RiscTransfer: #{from} -> #{to}"
"Transfer: #{from} -> #{to}"
end
end
def self.transfer( source , from , to)
RiscTransfer.new( source , from , to)
Transfer.new( source , from , to)
end
end

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@ -184,7 +184,7 @@ module Risc
true
end
def execute_RiscTransfer
def execute_Transfer
value = get_register @instruction.from
set_register @instruction.to , value
true

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@ -22,11 +22,11 @@ module Rubyx
LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant,
SlotToReg, RegToSlot, SlotToReg, LoadConstant, RegToSlot,
LoadConstant, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, RiscTransfer, FunctionCall, Label,
LoadConstant, RegToSlot, Transfer, FunctionCall, Label,
LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
RiscTransfer, Syscall, RiscTransfer, RiscTransfer, RegToSlot,
Label, FunctionReturn, RiscTransfer, SlotToReg, SlotToReg,
Label, FunctionReturn, RiscTransfer, Syscall, NilClass]
Transfer, Syscall, Transfer, Transfer, RegToSlot,
Label, FunctionReturn, Transfer, SlotToReg, SlotToReg,
Label, FunctionReturn, Transfer, Syscall, NilClass]
end
def test_overflow

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@ -21,7 +21,7 @@ HERE
check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant,
LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
end
@ -32,7 +32,7 @@ HERE
end
def pest_transfer
transfer = ticks 19
assert_equal RiscTransfer , transfer.class
assert_equal Transfer , transfer.class
assert_equal @interpreter.get_register(transfer.to) , @interpreter.get_register(transfer.from)
end

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@ -26,11 +26,11 @@ HERE
LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot,
RiscTransfer, FunctionCall, Label, LoadConstant, SlotToReg,
Transfer, FunctionCall, Label, LoadConstant, SlotToReg,
RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
SlotToReg, RegToByte, Label, FunctionReturn, RiscTransfer,
SlotToReg, RegToByte, Label, FunctionReturn, Transfer,
SlotToReg, SlotToReg, LoadConstant, SlotToReg, RegToSlot,
Label, FunctionReturn, RiscTransfer, Syscall, NilClass]
Label, FunctionReturn, Transfer, Syscall, NilClass]
end
def pest_branch

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@ -38,17 +38,17 @@ HERE
LoadConstant, RegToSlot, FunctionCall, Label, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, RiscTransfer, FunctionCall, Label,
LoadConstant, RegToSlot, Transfer, FunctionCall, Label,
LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
LoadConstant, OperatorInstruction, IsZero, SlotToReg, LoadConstant,
RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, RegToSlot, RiscTransfer, FunctionCall,
RegToSlot, LoadConstant, RegToSlot, Transfer, FunctionCall,
Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
SlotToReg, RiscTransfer, Syscall, RiscTransfer, RiscTransfer,
RegToSlot, Label, FunctionReturn, RiscTransfer, SlotToReg,
SlotToReg, Transfer, Syscall, Transfer, Transfer,
RegToSlot, Label, FunctionReturn, Transfer, SlotToReg,
SlotToReg, Branch, Label, Label, FunctionReturn,
RiscTransfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
Transfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
end
end

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@ -40,7 +40,7 @@ module Risc
check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant,
LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
end

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@ -22,7 +22,7 @@ HERE
check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant,
LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
check_return 0
end

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@ -21,7 +21,7 @@ HERE
check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant,
LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
check_return 0
end

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@ -21,12 +21,12 @@ HERE
check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, FunctionCall, Label, SlotToReg,
LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, LoadConstant, RegToSlot, RiscTransfer,
SlotToReg, RegToSlot, LoadConstant, RegToSlot, Transfer,
FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, RiscTransfer, Syscall, RiscTransfer,
RiscTransfer, RegToSlot, Label, FunctionReturn, RiscTransfer,
SlotToReg, SlotToReg, Transfer, Syscall, Transfer,
Transfer, RegToSlot, Label, FunctionReturn, Transfer,
SlotToReg, SlotToReg, LoadConstant, SlotToReg, RegToSlot,
Label, FunctionReturn, RiscTransfer, Syscall, NilClass]
Label, FunctionReturn, Transfer, Syscall, NilClass]
end
def pest_branch

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@ -25,11 +25,11 @@ HERE
LoadConstant, RegToSlot, FunctionCall, Label, SlotToReg,
LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, RiscTransfer, FunctionCall, Label,
LoadConstant, RegToSlot, Transfer, FunctionCall, Label,
LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, ByteToReg, RegToSlot, Label, FunctionReturn,
RiscTransfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
Transfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
end

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@ -30,12 +30,12 @@ HERE
LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant,
LoadConstant, OperatorInstruction, IsZero, SlotToReg, LoadConstant,
RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, RegToSlot, RiscTransfer, FunctionCall,
RegToSlot, LoadConstant, RegToSlot, Transfer, FunctionCall,
Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
SlotToReg, RiscTransfer, Syscall, RiscTransfer, RiscTransfer,
RegToSlot, Label, FunctionReturn, RiscTransfer, SlotToReg,
SlotToReg, Transfer, Syscall, Transfer, Transfer,
RegToSlot, Label, FunctionReturn, Transfer, SlotToReg,
SlotToReg, Branch, Label, LoadConstant, SlotToReg,
RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall,
RegToSlot, Label, FunctionReturn, Transfer, Syscall,
NilClass]
end
end