From b4489b109337f48ac04930edbb9ed1ab3663dd89 Mon Sep 17 00:00:00 2001 From: Torsten Ruger Date: Wed, 21 Mar 2018 15:48:04 +0530 Subject: [PATCH] rename RiscTransfer to Transfer --- lib/arm/translator.rb | 2 +- lib/risc/instructions/reg_to_slot.rb | 2 +- lib/risc/instructions/slot_to_reg.rb | 2 +- .../{register_transfer.rb => transfer.rb} | 10 +++++----- lib/risc/interpreter.rb | 2 +- stash/fragments/test_hello.rb | 8 ++++---- test/risc/interpreter/test_add.rb | 4 ++-- test/risc/interpreter/test_byte_to_reg.rb | 6 +++--- test/risc/interpreter/test_called_if.rb | 12 ++++++------ test/risc/interpreter/test_change.rb | 2 +- test/risc/interpreter/test_mult.rb | 2 +- test/risc/interpreter/test_plus.rb | 2 +- test/risc/interpreter/test_puts.rb | 8 ++++---- test/risc/interpreter/test_reg_to_byte.rb | 6 +++--- test/risc/interpreter/test_simple_if.rb | 8 ++++---- 15 files changed, 38 insertions(+), 38 deletions(-) rename lib/risc/instructions/{register_transfer.rb => transfer.rb} (78%) diff --git a/lib/arm/translator.rb b/lib/arm/translator.rb index c3217197..b308d7e0 100644 --- a/lib/arm/translator.rb +++ b/lib/arm/translator.rb @@ -31,7 +31,7 @@ module Arm ArmMachine.str( :lr , code.register , arm_index(code) ) end - def translate_RiscTransfer( code ) + def translate_Transfer( code ) # Risc machine convention is from => to # But arm has the receiver/result as the first ArmMachine.mov( code.to , code.from) diff --git a/lib/risc/instructions/reg_to_slot.rb b/lib/risc/instructions/reg_to_slot.rb index 655eb60e..ffe603bb 100644 --- a/lib/risc/instructions/reg_to_slot.rb +++ b/lib/risc/instructions/reg_to_slot.rb @@ -7,7 +7,7 @@ module Risc # This is because that is what cpu's can do. In programming terms this would be accessing # an element in an array, in the case of RegToSlot setting the register in the array. - # btw: to move data between registers, use RiscTransfer + # btw: to move data between registers, use Transfer class RegToSlot < Setter diff --git a/lib/risc/instructions/slot_to_reg.rb b/lib/risc/instructions/slot_to_reg.rb index 89391948..7ed5b7d8 100644 --- a/lib/risc/instructions/slot_to_reg.rb +++ b/lib/risc/instructions/slot_to_reg.rb @@ -7,7 +7,7 @@ module Risc # This is because that is what cpu's can do. In programming terms this would be accessing # an element in an array, in the case of SlotToReg setting the value in the array. - # btw: to move data between registers, use RiscTransfer + # btw: to move data between registers, use Transfer class SlotToReg < Getter diff --git a/lib/risc/instructions/register_transfer.rb b/lib/risc/instructions/transfer.rb similarity index 78% rename from lib/risc/instructions/register_transfer.rb rename to lib/risc/instructions/transfer.rb index f2445c59..fc955a49 100644 --- a/lib/risc/instructions/register_transfer.rb +++ b/lib/risc/instructions/transfer.rb @@ -1,6 +1,6 @@ module Risc - # transfer the constents of one register to another. + # Transfer the constents of one register to another. # possibly called move in some cpus # There are other instructions to move data from / to memory, namely SlotToReg and RegToSlot @@ -10,13 +10,13 @@ module Risc # Also it is used for moving temorary data # - class RiscTransfer < Instruction + class Transfer < Instruction # initialize with from and to registers. # First argument from # second argument to # # Note: this may be reversed from some assembler notations (also arm) - def initialize source , from , to + def initialize( source , from , to ) super(source) @from = from @to = to @@ -26,10 +26,10 @@ module Risc attr_reader :from, :to def to_s - "RiscTransfer: #{from} -> #{to}" + "Transfer: #{from} -> #{to}" end end def self.transfer( source , from , to) - RiscTransfer.new( source , from , to) + Transfer.new( source , from , to) end end diff --git a/lib/risc/interpreter.rb b/lib/risc/interpreter.rb index dd89a06b..4acdab3f 100644 --- a/lib/risc/interpreter.rb +++ b/lib/risc/interpreter.rb @@ -184,7 +184,7 @@ module Risc true end - def execute_RiscTransfer + def execute_Transfer value = get_register @instruction.from set_register @instruction.to , value true diff --git a/stash/fragments/test_hello.rb b/stash/fragments/test_hello.rb index c4cec86b..f584c767 100644 --- a/stash/fragments/test_hello.rb +++ b/stash/fragments/test_hello.rb @@ -22,11 +22,11 @@ module Rubyx LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg, RegToSlot, - LoadConstant, RegToSlot, RiscTransfer, FunctionCall, Label, + LoadConstant, RegToSlot, Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, - RiscTransfer, Syscall, RiscTransfer, RiscTransfer, RegToSlot, - Label, FunctionReturn, RiscTransfer, SlotToReg, SlotToReg, - Label, FunctionReturn, RiscTransfer, Syscall, NilClass] + Transfer, Syscall, Transfer, Transfer, RegToSlot, + Label, FunctionReturn, Transfer, SlotToReg, SlotToReg, + Label, FunctionReturn, Transfer, Syscall, NilClass] end def test_overflow diff --git a/test/risc/interpreter/test_add.rb b/test/risc/interpreter/test_add.rb index 3bebcad3..f2e338bd 100644 --- a/test/risc/interpreter/test_add.rb +++ b/test/risc/interpreter/test_add.rb @@ -21,7 +21,7 @@ HERE check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant, LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] end @@ -32,7 +32,7 @@ HERE end def pest_transfer transfer = ticks 19 - assert_equal RiscTransfer , transfer.class + assert_equal Transfer , transfer.class assert_equal @interpreter.get_register(transfer.to) , @interpreter.get_register(transfer.from) end diff --git a/test/risc/interpreter/test_byte_to_reg.rb b/test/risc/interpreter/test_byte_to_reg.rb index 9517073b..efaab7b5 100644 --- a/test/risc/interpreter/test_byte_to_reg.rb +++ b/test/risc/interpreter/test_byte_to_reg.rb @@ -26,11 +26,11 @@ HERE LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, - RiscTransfer, FunctionCall, Label, LoadConstant, SlotToReg, + Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, - SlotToReg, RegToByte, Label, FunctionReturn, RiscTransfer, + SlotToReg, RegToByte, Label, FunctionReturn, Transfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg, RegToSlot, - Label, FunctionReturn, RiscTransfer, Syscall, NilClass] + Label, FunctionReturn, Transfer, Syscall, NilClass] end def pest_branch diff --git a/test/risc/interpreter/test_called_if.rb b/test/risc/interpreter/test_called_if.rb index d739ae60..7c67b813 100644 --- a/test/risc/interpreter/test_called_if.rb +++ b/test/risc/interpreter/test_called_if.rb @@ -38,17 +38,17 @@ HERE LoadConstant, RegToSlot, FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, - LoadConstant, RegToSlot, RiscTransfer, FunctionCall, Label, + LoadConstant, RegToSlot, Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero, SlotToReg, LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, LoadConstant, RegToSlot, RiscTransfer, FunctionCall, + RegToSlot, LoadConstant, RegToSlot, Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, - SlotToReg, RiscTransfer, Syscall, RiscTransfer, RiscTransfer, - RegToSlot, Label, FunctionReturn, RiscTransfer, SlotToReg, + SlotToReg, Transfer, Syscall, Transfer, Transfer, + RegToSlot, Label, FunctionReturn, Transfer, SlotToReg, SlotToReg, Branch, Label, Label, FunctionReturn, - RiscTransfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + Transfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] end end diff --git a/test/risc/interpreter/test_change.rb b/test/risc/interpreter/test_change.rb index 7016ba5c..04375da4 100644 --- a/test/risc/interpreter/test_change.rb +++ b/test/risc/interpreter/test_change.rb @@ -40,7 +40,7 @@ module Risc check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant, LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] end diff --git a/test/risc/interpreter/test_mult.rb b/test/risc/interpreter/test_mult.rb index 8e8828d6..9a8d056e 100644 --- a/test/risc/interpreter/test_mult.rb +++ b/test/risc/interpreter/test_mult.rb @@ -22,7 +22,7 @@ HERE check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant, LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] check_return 0 end diff --git a/test/risc/interpreter/test_plus.rb b/test/risc/interpreter/test_plus.rb index 46745dae..b8cc0730 100644 --- a/test/risc/interpreter/test_plus.rb +++ b/test/risc/interpreter/test_plus.rb @@ -21,7 +21,7 @@ HERE check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant, LoadConstant, OperatorInstruction, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] check_return 0 end diff --git a/test/risc/interpreter/test_puts.rb b/test/risc/interpreter/test_puts.rb index 90f7efab..62e4cbe4 100644 --- a/test/risc/interpreter/test_puts.rb +++ b/test/risc/interpreter/test_puts.rb @@ -21,12 +21,12 @@ HERE check_chain [Branch, Label, LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, FunctionCall, Label, SlotToReg, LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant, - SlotToReg, RegToSlot, LoadConstant, RegToSlot, RiscTransfer, + SlotToReg, RegToSlot, LoadConstant, RegToSlot, Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, - SlotToReg, SlotToReg, RiscTransfer, Syscall, RiscTransfer, - RiscTransfer, RegToSlot, Label, FunctionReturn, RiscTransfer, + SlotToReg, SlotToReg, Transfer, Syscall, Transfer, + Transfer, RegToSlot, Label, FunctionReturn, Transfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg, RegToSlot, - Label, FunctionReturn, RiscTransfer, Syscall, NilClass] + Label, FunctionReturn, Transfer, Syscall, NilClass] end def pest_branch diff --git a/test/risc/interpreter/test_reg_to_byte.rb b/test/risc/interpreter/test_reg_to_byte.rb index b4aea38f..ab382295 100644 --- a/test/risc/interpreter/test_reg_to_byte.rb +++ b/test/risc/interpreter/test_reg_to_byte.rb @@ -25,11 +25,11 @@ HERE LoadConstant, RegToSlot, FunctionCall, Label, SlotToReg, LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, - LoadConstant, RegToSlot, RiscTransfer, FunctionCall, Label, + LoadConstant, RegToSlot, Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, ByteToReg, RegToSlot, Label, FunctionReturn, - RiscTransfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + Transfer, SlotToReg, SlotToReg, LoadConstant, SlotToReg, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] end diff --git a/test/risc/interpreter/test_simple_if.rb b/test/risc/interpreter/test_simple_if.rb index 9f3bc647..ebd699cc 100644 --- a/test/risc/interpreter/test_simple_if.rb +++ b/test/risc/interpreter/test_simple_if.rb @@ -30,12 +30,12 @@ HERE LoadConstant, RegToSlot, FunctionCall, Label, LoadConstant, LoadConstant, OperatorInstruction, IsZero, SlotToReg, LoadConstant, RegToSlot, LoadConstant, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, LoadConstant, RegToSlot, RiscTransfer, FunctionCall, + RegToSlot, LoadConstant, RegToSlot, Transfer, FunctionCall, Label, LoadConstant, SlotToReg, RegToSlot, SlotToReg, - SlotToReg, RiscTransfer, Syscall, RiscTransfer, RiscTransfer, - RegToSlot, Label, FunctionReturn, RiscTransfer, SlotToReg, + SlotToReg, Transfer, Syscall, Transfer, Transfer, + RegToSlot, Label, FunctionReturn, Transfer, SlotToReg, SlotToReg, Branch, Label, LoadConstant, SlotToReg, - RegToSlot, Label, FunctionReturn, RiscTransfer, Syscall, + RegToSlot, Label, FunctionReturn, Transfer, Syscall, NilClass] end end