rename RiscTransfer to Transfer

2018-03-21 15:48:04 +05:30
parent fa797f722d
commit b4489b1093
15 changed files with 38 additions and 38 deletions
--- a/lib/risc/instructions/slot_to_reg.rb
+++ b/lib/risc/instructions/slot_to_reg.rb
@ -7,7 +7,7 @@ module Risc
  # This is because that is what cpu's can do. In programming terms this would be accessing
  #  an element in an array, in the case of SlotToReg setting the value in the array.

-  # btw: to move data between registers, use RiscTransfer
+  # btw: to move data between registers, use Transfer

  class SlotToReg < Getter