fix test_exit registers
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@ -17,8 +17,8 @@ module SlotMachine
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merge_label = Risc.label("merge" , "merge_label_#{object_id}")
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merge_label = Risc.label("merge" , "merge_label_#{object_id}")
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result = Risc::RegisterValue.new(:result , :Object)
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result = Risc::RegisterValue.new(:result , :Object)
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builder.build do
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builder.build do
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left = message[:receiver].to_reg.reduce_int
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left = message[:receiver].to_reg.reduce_int(false) #false == hack
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right = message[:arg1].to_reg.reduce_int
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right = message[:arg1].to_reg.reduce_int(false)
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if(operator.to_s.start_with?('<') )
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if(operator.to_s.start_with?('<') )
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right.op :- , left
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right.op :- , left
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@ -16,7 +16,6 @@ module SlotMachine
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def test_risc_length
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def test_risc_length
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assert_equal 25 , @method.to_risc.risc_instructions.length
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assert_equal 25 , @method.to_risc.risc_instructions.length
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end
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end
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#TODO, check the actual instructions, at least by class
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end
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end
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class TestIntComp2Risc < BootTest
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class TestIntComp2Risc < BootTest
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def setup
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def setup
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@ -34,12 +33,12 @@ module SlotMachine
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end
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end
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def test_all
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def test_all
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assert_slot_to_reg 1 , :message , 2 , "message.receiver"
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assert_slot_to_reg 1 , :message , 2 , "message.receiver"
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assert_slot_to_reg 2 , "message.receiver" , 2 , "message.receiver"
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assert_slot_to_reg 2 , "message.receiver" , 2 , "message.receiver.data_1"
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assert_slot_to_reg 3 ,:message , 9 , "message.arg1"
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assert_slot_to_reg 3 ,:message , 9 , "message.arg1"
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assert_slot_to_reg 4 , "message.arg1" , 2 , "message.arg1"
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assert_slot_to_reg 4 , "message.arg1" , 2 , "message.arg1.data_1"
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assert_operator 5 , :- , "message.receiver" , "message.arg1"
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assert_operator 5 , :- , "message.receiver.data_1" , "message.arg1.data_1"
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assert_minus 6 , "false_label_"
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assert_minus 6 , "false_label_"
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assert_zero 7 , "false_label_"
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assert_not_zero 7 , "false_label_"
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assert_load 8 , Parfait::TrueClass , :result
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assert_load 8 , Parfait::TrueClass , :result
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assert_branch 9 , "merge_label_"
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assert_branch 9 , "merge_label_"
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assert_label 10 , "false_label_"
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assert_label 10 , "false_label_"
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@ -15,22 +15,21 @@ module SlotMachine
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assert_equal Risc::MethodCompiler , @method.to_risc.class
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assert_equal Risc::MethodCompiler , @method.to_risc.class
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end
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end
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def test_risc_length
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def test_risc_length
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assert_equal 40 , @method.to_risc.risc_instructions.length
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assert_equal 39 , @method.to_risc.risc_instructions.length
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end
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end
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def test_allocate
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def test_allocate
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assert_allocate
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assert_allocate
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end
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end
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def test_all
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def test_all
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assert_reg_to_slot risc(23) , :r1 , :r0 , 5
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assert_reg_to_slot 23 , "id_factory_.next_object" , :message , 5
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assert_transfer risc(24) , :r0 , :r8
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assert_transfer 24 , :message , :saved_message
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assert_slot_to_reg risc(25),:r0 , 5 , :r0
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assert_slot_to_reg 25 ,:message , 5 , :message
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assert_slot_to_reg risc(26),:r0 , 2 , :r0
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assert_slot_to_reg 26 ,:message , 2 , "message.data_1"
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assert_equal Risc::Syscall, risc(27).class
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assert_syscall 27 , :exit
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assert_equal :exit , risc(27).name
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assert_slot_to_reg 28 ,:message , 5 , "message.return_value"
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assert_slot_to_reg risc(28),:r0 , 5 , :r2
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assert_reg_to_slot 29 , "message.return_value" , :message , 5
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assert_reg_to_slot risc(29) , :r2 , :r0 , 5
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assert_branch 30 , "return_label"
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assert_branch risc(30) , "return_label"
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assert_label 31 , "return_label"
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assert_label risc(31) , "return_label"
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end
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end
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def test_return
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def test_return
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assert_return(31)
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assert_return(31)
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@ -1,4 +1,12 @@
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module Risc
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module Risc
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module HasCompiler
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def risc(i)
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assert @compiler , "no compiler"
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instructions = @compiler.risc_instructions
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return instructions if i == 0
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instructions.next(i)
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end
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end
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class FakeCallable
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class FakeCallable
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def self_type
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def self_type
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Parfait.object_space.types.values.first
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Parfait.object_space.types.values.first
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